emPC-CXR
(
Hardware Manual
)
•
FPGA expansion subsystem
6 - 25
Rev. V1.2
©
Janz Tec AG
If a CAN interrupt request line is disabled, then the corresponding bit is
forced to “1”.
COM[1..0]
Interrupt status info. Each defined bit in this register reflects the status of
the INT# pin of the corresponding COM. A one will be read when an
interrupt is pending.
If a COM interrupt request line is disabled, then the corresponding bit is
forced to “0”.
Reserved
Reserved positions are undefined, and must not be considered. Software
must mask them off.
Interrupt requests can be masked off by the CPU. This is done through the interrupt disable/enable
registers. Interrupts are disabled after RESET, and you need to enable a CAN interrupt line before
using it.
INT_ DISABLE
BAR4 +
0x8 (32bit, wo)
31..10
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
INT_ENABLE
BAR4 +
0xC (32bit, wo)
31..10
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
6.1.3
Function Reset
To ensure a defined state of a function at any time, it is possible to activate the RST# line of a function
via software. This can be done with the reset assert/deassert registers. The RST# line of all functions
are activated during a PCIe bus reset.
RESET_ASSERT
BAR4 +
0x10 (32bit, wo)
31..10
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
RESET_DEASSERT
BAR4 +
0x14 (32bit, wo)
31..10
9
8
7..2
1
0
reserved
COM1
COM0
Reserved
CAN1
CAN0
6.1.4
Internal I
2
C bus
The control register for the onboard I
2
C interface provides bit-bang style I2C implementation.
CAN[1..0]
COM[1..0]
Writing one of the bits disables/enables interrupts from the corresponding
function. Both registers are accessed in hot-1 technique: Writing a one to
a bit disables/enables further interrupts from the corresponding function,
writing zero to a bit do not affect the interrupt mask status of that function.
If a functions interrupt request line is disabled, then this functions
interrupt bit will never appear in the INT_STAT register and it will not
cause interrupts.
Reserved
Reserved bit positions must be written as zero.
CAN[1..0]
COM[1..0]
Writing one of the bits disables/enables interrupts from the corresponding
function. Both registers are accessed in hot-1 technique: Writing a one to
a bit disables/enables further interrupts from the corresponding function,
writing zero to a bit do not affect the interrupt mask status of that function.
If a functions interrupt request line is disabled, then this functions
interrupt bit will never appear in the INT_STAT register and it will not
cause interrupts.
Reserved
Reserved bit positions must be written as zero.
