emPC-CXR
(
Hardware Manual
)
•
FPGA expansion subsystem
6 - 27
Rev. V1.2
©
Janz Tec AG
RESET:
-
0
-
1
1
1
-
0
6.3
Serial Port Interface
6.3.1
Serial Port address space
The UART controllers are mapped into memory address space
Address Offset
accesses:
BAR2 + 0x1000..0x1008
UART 0
BAR2 + 0x1100..0x1108
UART 1
The serial port UARTs are implemented inside the FPGA and are 16550 compatible (16 bytes FIFO).
On customer request other serial port options are possible, but
not yet
implemented:
•
The COM Express Typ 6 defined serial ports (Rx/TX only) can be routed to the
connectors. Implementation depends on availability on the COM Express
module. Sometimes such ports are available as legacy ports, sometimes as USB
based ports, sometimes as custom ports, sometimes they are not available at all.
•
LPC based legacy serial ports (IO address) can be implemented in FPGA if
legacy ports are required for software compatibility. BIOS support for such ports
can be a difficult issue however.
