6 - 30
emPC-CXR
(
Hardware Manual
)
•
FPGA expansion subsystem
©
Janz Tec AG
Rev. V1.2
6.6
FPGA Reprogramming
An interface is provided to reprogram the SPI Flash of the FPGA.
SPI_RX
BAR0 +
0x100 (32bit, ro)
31..0
RX_DATA
RX_DATA
Data read from SPI FLASH. Data is shifted in at LSB.
SPI_TX
BAR0 +
0x104 (32bit, rw)
31..0
TX_DATA
TX_DATA
Data to be written to SPI FLASH. Data is shifted out when SPI_TX is
written and the controller is enabled (EN=1). MSB is shifted out first.
SPI_CONTROL
BAR0 +
0x108 (32bit, rw)
31..25
24.20
19..14
14
13
12
11..1
0
Reserved
SHIFT
Reserved
WP
HOLD
CS
Reserved
EN
RESET:
-
0
-
1
1
1
-
0
EN
1=enable SPI controller.
CS
SPI FLASH chip select control (0=low)
HOLD
SPI FLASH HOLD# control (0=low)
WP
SPI FLASH WP# control (0=low)
SHIFT
Data shift count. N+1 bits are shifted out when SPI_TX is written.
Reserved
Reserved positions are undefined, and must not be considered. Write
reserved bit as zero.
SPI_STATUS
BAR0 +
0x114 (32bit, ro)
31..8
7
6..3
2
1
0
Reserved
TC
Reserved
TF
Reserved
TE
RESET:
-
1
-
0
-
1
TE
Transmitter empty flag (1=empty)
TF
Transmitter full flag (1=full)
TC
Transfer complete (0=busy, 1=done)
Reserved
Reserved positions are undefined, and must not be considered.