emPC-CXR
(
Hardware Manual
)
•
FPGA expansion subsystem
6 - 29
Rev. V1.2
©
Janz Tec AG
6.5
Digital IO
Programming the digital IO is utilized by reading/writing register in the FPGA register space.
Address Offset
access
Description
BAR5 + 0x00
-
-
BAR5 + 0x01
RW
DIGIO_OUT
BAR5 + 0x02
WO
DIGIO_IN
BAR5 + 0x03
RO
DIGIO_STAT
Table 14: Digital IO registers
DIGIO_OUT
BAR5+0x1 (byte, rw)
7
6
5
4
3
2
1
0
write
0, read as don’t care
OUT3 OUT2 OUT1 OUT0
DIGIO_IN
BAR5+0x2 (byte, ro)
7
6
5
4
3
2
1
0
IN3
IN2
IN1
IN0
read as don’t care
IN3..0
OUT3..0
status of the digital input line
0: input voltage 0..4V
1: input voltage 9..24V
DIGIO_STATUS
BAR5+0x3 (byte, ro)
7
6
5
4
3
2
1
0
NO
NO
1: Normal operation.
0: Overheat condition; the output port is shutting down. This may result in
cooling down the chip which sets the NO flag back to 1. If the error still
exists, the chip will heat up again and the NO flag will be set to 0.
