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Pro II: Zusatz- und Schnittstellenmodule
Pro II-SPI-2 Rev. E
ADwin
212
ADwin-Pro II
Hardware, manual Dec. 2018
Pro II-SPI-2-D (differential signals)
In operation mode digital module, 8 digital channels with TTL levels and 12 dif-
ferential channels are available. With SPI operation modes, the 8 digital TTL
channels and 4 differential channels are available.
The channels with TTL levels can be configured in groups of 4 as inputs or out-
puts using the instruction
P2_DigProg
. The differential digital channels can
be individually configured as inputs or outputs with
P2_DigProg_Bits
. The
channels are configured as inputs after power up.
Please note, that instructions for digital channels of the module Pro II-SPI-2-D
are valid for both channels with TTL signals and channels with differential sig-
nals. As an example
P2_Digout_Long
will set differential signals with bits
0…11 and TTL signals with bits 16…19 / 24…27 (as far as they were config-
ured as outputs). The bits 12…15, 20…23, and 28…31 are not used here.
Hardware
The pin assignment depends on the current operation mode of the module
(
P2_SPI_Mode
).
If you have problems with shielding of unused
DataIn
/
DataOut
lines, it may
help to connect the pins to logical 0 or
DGND
.
Pro II-SPI-2-T
SPI-2-T: Master 1 + Master 2
SPI-2-T: Master 1 + Slave 2
SPI-2-T: Slave 1 + Slave 2
SPI-2-T: Digital
DIG I/O, BIT 1
DIG I/O, BIT 3
DIG I/O, BIT 5
DIG I/O, BIT 7
DIGIN, BIT 9
DataIn2 Master
DIGIN, BIT 13
DIGIN, BIT 15
SS1 out
DIGOUT, BIT 19
DIGOUT, BIT 21
DIGOUT, BIT 23
SS2 out
DIGOUT, BIT 27
DIGOUT, BIT 29
DIGOUT, BIT 31
DGND
EVENT IN
DIG I/O, BIT 0
DIG I/O, BIT 2
DIG I/O, BIT 4
DIG I/O, BIT 6
DataIn1 Master
DIGIN, BIT 10
DIGIN, BIT 12
DIGIN, BIT 14
DataOut 1 Master
SCLK1 out
DIGOUT, BIT 20
DIGOUT, BIT 22
DataOut 2 Master
SCLK2 out
DIGOUT, BIT 28
DIGOUT, BIT 30
DGND
+5V (OUT, <0.1A)
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
DIG I/O, BIT 1
DIG I/O, BIT 3
DIG I/O, BIT 5
DIG I/O, BIT 7
DIGIN, BIT 9
DataIn2 Slave
SCLK2 in, Slave
DIGIN, BIT 15
SS1 out
DIGOUT, BIT 19
DIGOUT, BIT 21
DIGOUT, BIT 23
RESERVED
RESERVED
RESERVED
RESERVED
DGND
EVENT IN
DIG I/O, BIT 0
DIG I/O, BIT 2
DIG I/O, BIT 4
DIG I/O, BIT 6
DataIn1 Master
DIGIN, BIT 10
SS2 in, Slave
DIGIN, BIT 14
DataOut 1 Master
SCLK1 out
DIGOUT, BIT 20
DIGOUT, BIT 22
DataOut 2 Slave
RESERVED
RESERVED
RESERVED
DGND
+5V (OUT, <0.1A)
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
DIG I/O, BIT 1
DIG I/O, BIT 3
DIG I/O, BIT 5
DIG I/O, BIT 7
SS1 in, Slave
DataIn2 Slave
SCLK2 in, Slave
DIGIN, BIT 15
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DGND
EVENT IN
DIG I/O, BIT 0
DIG I/O, BIT 2
DIG I/O, BIT 4
DIG I/O, BIT 6
DataIn1 Slave
SCLK1 in, Slave
SS2 in, Slave
DIGIN, BIT 14
DataOut 1 Slave
RESERVED
RESERVED
RESERVED
DataOut 2 Slave
RESERVED
RESERVED
RESERVED
DGND
+5V (OUT, <0.1A)
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
DIG I/O, BIT 1
DIG I/O, BIT 3
DIG I/O, BIT 5
DIG I/O, BIT 7
DIG I/O, BIT 9
DIG I/O, BIT 11
DIG I/O, BIT 13
DIG I/O, BIT 15
DIG I/O, BIT 17
DIG I/O, BIT 19
DIG I/O, BIT 21
DIG I/O, BIT 23
DIG I/O, BIT 25
DIG I/O, BIT 27
DIG I/O, BIT 29
DIG I/O, BIT 31
DGND
EVENT IN
DIG I/O, BIT 0
DIG I/O, BIT 2
DIG I/O, BIT 4
DIG I/O, BIT 6
DIG I/O, BIT 8
DIG I/O, BIT 10
DIG I/O, BIT 12
DIG I/O, BIT 14
DIG I/O, BIT 16
DIG I/O, BIT 18
DIG I/O, BIT 20
DIG I/O, BIT 22
DIG I/O, BIT 24
DIG I/O, BIT 26
DIG I/O, BIT 28
DIG I/O, BIT 30
DGND
+5V (OUT, <0.1A
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20