Pro II: Zusatz- und Schnittstellenmodule
Pro II-SPI-2 Rev. E
ADwin
210
ADwin-Pro II
Hardware, manual Dec. 2018
SPI signals
The SPI signals of the module ADwin-Pro II-SPI-2-T use 5 V TTL levels, the
signals of the module ADwin-Pro II-SPI-2-D are differential.
The SPI interfaces run with a bus frequency of max. 12.5 MHz.
In theory, an unlimited number of members can be connected to the SPI bus
while there has to be exactly one SPI master. The master creates the clock sig-
nal on the
SPI
CLK
line and selects via a
Slave
Select
(
SS
) line the slave
he will communicate with. If the master pulls
SS
to the appropriate TTL level,
the slave is activated, listens to
SPI
MOSI
and sends its data to
SPI
MISO
with
the clock rate of
SPI
CLK
, normally within the same data transfer.
Thus, an SPI message is transferred from master to slave (MOSI: master out,
slave in) and another SPI message from slave to master (MISO: master in,
slave out). The data transfer can happen in both directions at the same time.
The length of SPI messages can be configured freely, the maximum length of
an SPI message is 64 bits (= 8 Byte).
With each clock signal, a bit of the SPI message is transferred. A common data
byte requires 8 clock periods to be completely transferred. You can configure
if a data transfer starts with the most (MSB) or the least significant bit (LSB).
The data transfer is completed when the master permanently deactivates the
slave select line.
You can insert a waiting time into the clock signal
SCLK
of the SPI master. As
well you can insert a time delay for reading the MISO signal.
Generally, the slave select signal
SS
out
of the master ends a defined time
before the start of the clock signal
SCLK
and ends by the same time after the
end of the clock signal. You can extend this time interval by software.
Interface SPI master
The module Pro II-SPI-2 Rev. E provides the following lines / signals for the
communication as SPI master. The numbers 1 and 2 refer to the numbers of
the interfaces:
Signal
Description
SCLK1 out
SCLK2 out
Outgoing clock signal (SPI clock) being created by the appro-
priate master. The maximum SPI clock rate is 12.5 MHz.
The real maximum clock rate depends on the used cable
length.
SS1 out
SS2 out
Outgoing slave select signal to activate connected SPI slaves
for the currently valid SPI message.
The single slave select line
SS
out
is used in automatic activa-
tion mode; with manual activation further slave select lines can
be used.
DATAOUT1
DATAOUT2
Data line from master to slave: Master Out, Slave In (MOSI).
DATAIN1
DATAIN2
Data line from slave to master: Master In, Slave Out (MISO).
