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Pro II: Digital-I/O Modules
Pro II-DIO-32-TiCo2 Rev. E
ADwin
116
ADwin-Pro II
Hardware, manual Dec. 2018
Fig. 99 – Pro II-DIO-32-TiCo2 Rev. E: Block diagram
Fig. 100 – Pro II-DIO-32-TiCo2 Rev. E: Front panel and Pin assignment
Input/output channels
32; programmable via software as inputs/outputs in
blocks of 8
Pull down resistor
10k
Ω
Voltage thresholds
V
IL max
: 0.3×V
cc
; V
IH min
: 0.7×V
cc
with V
cc
= set voltage level
Voltage range
-0.5V … +5.5V
Output current
max. ±35mA per channel, max. ±70mA per block
(8 channels) via V
CC
or GND
Event input
TTL logic
Power up status
All channels as inputs
Input / output FIFO
Size: 2048 value pairs
Frequency: 200MHz
TiCo
Prozessor type: TiCo2
Clock rate: 100MHz
Memory size: 128kiB PM internal, 512KiB DM
internal
Connector
37-pin D-Sub female connector
Fig. 101 – Pro II-DIO-32-TiCo2 Rev. E: Specification
DIO 32 RB
ADwi
n-P
ro
bus
0
1
31
...........
..........................
2
3
30
EVENT
Data
Register
Data
10k
10k
10k
10k
10k
10k
10k
Bus-
Trans-
ceiver
D00:07
Bus-
Trans-
ceiver
D08:15
Bus-
Trans-
ceiver
D16:23
Bus-
Trans-
ceiver
D24:31
DIG I/O, BIT 1
DIG I/O, BIT 3
DIG I/O, BIT 5
DIG I/O, BIT 7
DIG I/O, BIT 9
DIG I/O, BIT 11
DIG I/O, BIT 13
DIG I/O, BIT 15
DIG I/O, BIT 17
DIG I/O, BIT 19
DIG I/O, BIT 21
DIG I/O, BIT 23
DIG I/O, BIT 25
DIG I/O, BIT 27
DIG I/O, BIT 29
DIG I/O, BIT 31
DGND
EVENT IN
DIG I/O, BIT 0
DIG I/O, BIT 2
DIG I/O, BIT 4
DIG I/O, BIT 6
DIG I/O, BIT 8
DIG I/O, BIT 10
DIG I/O, BIT 12
DIG I/O, BIT 14
DIG I/O, BIT 16
DIG I/O, BIT 18
DIG I/O, BIT 20
DIG I/O, BIT 22
DIG I/O, BIT 24
DIG I/O, BIT 26
DIG I/O, BIT 28
DIG I/O, BIT 30
DGND
+5V, <100mA (fused)
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
DIO 32
TiCo2