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ADwin-Pro II
Hardware, manual Dec. 2018
143
Pro II: Digital-I/O Modules
Pro II-CNT-x Rev. E
ADwin
Pin assignment Pro II-CNT-T
Pin assignment Pro II-CNT-D
Pin assignment Pro II-CNT-I
Counter
4 multi-purpose counters
Cnt-D: 2 SSI decoders in addition
Counter resolution
32 bit
Event input
1
Reference clock
50MHz
Clock frequency four edge evaluation 12.5MHz max. (at 90° phase-shift of
the signals)
Clock frequency up/down counter
CNT-T: 25MHz max.
CNT-I, CNT-D: 15MHz max.
Reference frequency PWM analysis
100MHz
Connector
37-pin D-Sub female connector
TiCo
Prozessor type: TiCo1
Clock rate: 50MHz
Memory size: 28kiB PM internal,
28kiB DM internal
Power consumption
CNT-T approx. 150mA
CNT-D approx. 200mA
CNT-I approx. 200mA
Fig. 129 – Pro II-CNT-x Rev. E: General specification
CNTR 1 DIR
CNTR 1 B
RESERVED
RESERVED
CNTR 2 DIR
CNTR 2 B
RESERVED
RESERVED
CNTR 3 DIR
CNTR 3 B
RESERVED
RESERVED
CNTR 4 DIR
CNTR 4 B
RESERVED
RESERVED
DGND
EVENT IN
CNTR 1 CLR/LATCH
CNTR 1 CLK
CNTR 1 A
RESERVED
CNTR 2 CLR/LATCH
CNTR 2 CLK
CNTR 2 A
RESERVED
CNTR 3 CLR/LATCH
CNTR 3 CLK
CNTR 3 A
RESERVED
CNTR 4 CLR/LATCH
CNTR 4 CLK
CNTR 4 A
RESERVED
DGND
+5V (OUT, <0.1A)
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SSI 1, CLK (-)
CNTR 1, A/CLK (-)
CNTR 1, B/DIR (-)
CNTR 1, CLR/LATCH (-)
SSI 1, DATA (-)
CNTR 2, A/CLK (-)
CNTR 2, B/DIR (-)
CNTR 2, CLR/LATCH (-)
SSI 2, CLK (-)
CNTR 3, A/CLK (-)
CNTR 3, B/DIR (-)
CNTR 3, CLR/LATCH (-)
SSI 2, DATA (-)
CNTR 4, A/CLK (-)
CNTR 4, B/DIR (-)
CNTR 4, CLR/LATCH (-)
DGND
EVENT IN (+)
SSI 1, CLK (+)
CNTR 1, A/CLK (+)
CNTR 1, B/DIR (+)
CNTR 1, CLR/LATCH (+)
SSI 1, DATA (+)
CNTR 2, A/CLK (+)
CNTR 2, B/DIR (+)
CNTR 2, CLR/LATCH (+)
SSI 2, CLK (+)
CNTR 3, A/CLK (+)
CNTR 3, B/DIR (+)
CNTR 3, CLR/LATCH (+)
SSI 2, DATA (+)
CNTR 4, A/CLK (+)
CNTR 4, B/DIR (+)
CNTR 4, CLR/LATCH (+)
DGND
+5V (OUT, <0.1A)
EVENT IN (-)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
RESERVED
CNTR 1, A/CLK (-)
CNTR 1, B/DIR (-)
CNTR 1, CLR/LATCH (-)
RESERVED
CNTR 2, A/CLK (-)
CNTR 2, B/DIR (-)
CNTR 2, CLR/LATCH (-)
RESERVED
CNTR 3, A/CLK (-)
CNTR 3, B/DIR (-)
CNTR 3, CLR/LATCH (-)
RESERVED
CNTR 4, A/CLK (-)
CNTR 4, B/DIR (-)
CNTR 4, CLR/LATCH (-)
RESERVED
EVENT IN (+)
RESERVED
CNTR 1, A/CLK (+)
CNTR 1, B/DIR (+)
CNTR 1, CLR/LATCH (+)
RESERVED
CNTR 2, A/CLK (+)
CNTR 2, B/DIR (+)
CNTR 2, CLR/LATCH (+)
RESERVED
CNTR 3, A/CLK (+)
CNTR 3, B/DIR (+)
CNTR 3, CLR/LATCH (+)
RESERVED
CNTR 4, A/CLK (+)
CNTR 4, B/DIR (+)
CNTR 4, CLR/LATCH (+)
RESERVED
RESERVED
EVENT IN (-)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20