IXYS Zilog S3 Series, Руководство пользователя

Страница: 26 / 27

UM026704-0816 23
S3F80QB Development Kit
User Manual
Figure 22. S3F80QB Development Board Schematic Diagram, #2 of 2
VCC_5V
VCC_T PWR ON
DBG
Z_UART
NOT POPULATED
SCK0
MOSI0
VCC_T
Z_DBG
Z_RST
Z_RST
Z_DBG
Z_RST
XOUT XIN
XIN
XOUT
VCC_5V
VCC_T
VCC_T
VCC_T
S3_SCK
S3_SO
S3_SI
S3_SSN
C8
4.7uF
J16
1x6 RT-ANGL
1
2
3
4
5
6
J14
1
Z8F6481AN
U4
PA2
/DE0
/CL
K
2
IN/X2
IN
1
PA3
/CTS0
-/X2
O
UT
2
PE3
/T4
CHA/ESO
UT0
3
PD6
/DE1
4
PA4
/RXD0
/M
O
SI0
5
PA5
/TXD0
/SCK0
6
PD5
/TXD1
7
PA6
/T1
IN/T1
O
U
T-/SCL
8
PC4
/M
O
SI0
/T
0
IN/T
0
O
UT
-/SCL
/DE0
9
PC5
/SCK0
/T0
O
UT
/SDA/CT
S
0
-
10
PA7
/T1
O
UT/SDA
11
PD4/RXD1
12
PC6/T2IN/T2OUT-/SCKOUT/ESOUT0
13
PC7/T2OUT/CTS1-/ESOUT1
14
VDD
15
PD0/RESET-
16
DBG
17
PD3/C1OUT/AMPBOUT/ANA8
18
VSS
19
PC0/ANA4/VBIAS/C0INP
21
PC1/MISO0/ANA5/C0INN
22
PC2
/ANA3
/SS0
-
23
P
C
3/
M
IS
O
0/
A
N
A
11/
D
A
C
24
PD2
/C1
INP/AM
PBINP/ANA6
25
PD1
/C1
INN/AM
PBINN/ANA7
26
PB0
/ANA0
/AM
PAO
UT
27
PB1
/ANA1
/AM
P
AINN
28
PB2
/ANA2
/AM
PAINP
29
PB4
/VREF+
30
PB3
/VREF-
31
PE5
/T
4
CHC/ESOUT
2
32
PE6
/T
4
CHD/ESOUT
3
33
PE2/T4IN
34
VCORE
35
AVDD
36
VDD
37
PA0/T0IN/T0OUT-/CLKIN/XIN
38
PA1/T0OUT/XOUT
39
VSS
40
AVSS
41
PD7/C0OUT
42
PE1/DM/T0OUT
43
PE0/DP/T0IN/T0OUT-
44
PE4/T4CHB/ESOUT1
20
C9
0.1uF
R21
19.6K
C6
4.7uF
C13
0.1uF
R20
27
R17
16.5K
J13
1
R19
27
L1
FERRITE BEAD
C4
1uF
P1
USB, mini B
VBUS
1
DM
2
DP
3
ID
4
GND
5
SH1
6
SH2
7
SH3
8
SH4
9
h1
10
h2
11
Y2
24.000MHZ
C14
12pF
R16
470
D10
GREEN
2 1
J11
1
C5
1uF
C15
12pF
R18
20K
1
3
2
C7
0.1uF
J15
HDR/PIN 2x3
1 2
3 4
5 6
J12
1
C10
0.01uF
R23
10K
C11
0.01uF
U3
MIC5318
GND
2
EN
1
IN
3
ADJ
5
OUT
4
BYP
6
Center Pad
7
R22
10K
C12
4.7uF