Chapter 5 BIOS Setup
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WA133 Series
5.5.2 SDRAM Cycle Time Tras/Trc
This controls the number of SDRAM clocks used per access cycle.
Options
6/8 (*)
5/7
5.5.3 SDRAM RAS-to-CAS Delay
This controls the number of clocks between the SDRAM active command and the read / write
command.
Options
2
3 (*)
5.5.4 SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM
refresh, the refresh may be incomplete and the DRAM may fail to retain data. This controls the
idle(delay) clocks after issueing a prechange command to the SDRAM.
Options
2
3 (*)
5.5.5 System BIOS Cacheable
When enabled, accesses to the system BIOS will be cached.
Options
Enabled (*)
Disabled
5.5.6 Video BIOS Cacheable
When enabled, access to the video BIOS will be cached.
Options
Enabled (*)
Disabled
5.5.7 Memory Hole At 15M-16M
Some add-in cards need to re-map its resource to a block of main memory address range. Any
host cycles that match this memory hole are passed on to the add-in cards.
Options
Enabled
Disabled (*)
5.5.8 CPU Latency Timer
Configuration options: Enabled
Disabled (*)
5.5.9 Delayed Transaction
When enabled, the south bridge ICH will supports the Delayed Transaction mechanism when it
is the target of a PCI transaction.
Options
Enabled (*)
Disabled