REL1.0
Page 75 of 106
RZ/G1H Qseven Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No
Signal Name
Signal Type /
Termination
Description
44
Q7_GPIO5_(GP2_17)
IO, 3.3V CMOS
Qseven General purpose Input/Output5.
This pin is connected to control the LVDS
Backlight Power.
Note: This pin is connected to RZ/G1H CPU
GPIO line GP2_17 through Qseven MXM
connector 190
th
pin through default populated
resistor.
45
Q7_GPIO2_(GP0_26)
I, 3.3V CMOS/
10K PU
Qseven General purpose Input/Output2.
This pin is connected from Audio IN Jack for
Headphone Mic detect.
Note: This pin is also connected to RZ/G1H CPU
GPIO line GP0_26 through Qseven MXM
connector 187th pin through default populated
resistor.
46
MSIOF0_RXD(GP5_17)
I, 3.3V CMOS
SPI Master In Slave Out.
This Pin is used for On Board SPI Flash.
Note: This pin is connected to RZ/G1H CPU
MSIOF0_RXD line through Qseven MXM
connector 201st pin.
47
Q7_GPIO4_(GP1_28)
IO, 3.3V CMOS
Qseven General purpose Input/Output4.
This pin is connected to CAN0 Transceiver
Power down control.
Note: This pin is connected to RZ/G1H CPU
GPIO line GP1_28 through Qseven MXM
Connector 189th pin.
48
MSIOF0_TXD/MDT1(GP5_15)
O, 3.3V CMOS
SPI Master Out Slave In.
This pin is used for On Board SPI Flash.
Note: This pin is connected to RZ/G1H CPU
MSIOF0_TXD line through Qseven MXM
connector 199th pin.
49
MSIOF0_SS1/MD0(GP5_14)
I, 3.3V CMOS
SPI Chip Select2.
Note: This pin is connected to RZ/G1H CPU
MSIOF0_SS1 line through Qseven MXM
connector 202nd pin.
50
GND
Power
Ground.
51
MSIOF0_SCK(GP5_12)
I, 3.3V CMOS
SPI Clock.
This Pin is used for On Board SPI Flash.
Note: This pin is connected to RZ/G1H CPU
MSIOF0_SCK line through Qseven MXM
connector 203rd pin.
52
-
Not used in RZ/G1H carrier board.
Note: This pin is connected to Qseven MXM
connector 138
th
pin.
