Intel® Server Board S5500HV/Intel® Server System SR1670HV TPS
Functional Architecture
17
Intel Confidential
Revision 1.2
Intel order number E69391-006
Table 5 Memory Population Table
CPU 1 Configuration
DIMM_A2
DIMM_A1
DIMM_B2
DIMM_B1
DIMM_C2
DIMM_C1
1 DIMM
-
;
- - - -
2 DIMMs
-
;
-
;
- -
3 DIMMs
-
;
-
;
-
;
4 DIMMs
;
;
-
;
-
;
6 DIMMs
;
;
;
;
;
;
CPU 2 Configuration
DIMM_D2
DIMM_D1
DIMM_E2
DIMM_E1
DIMM_F2
DIMM_F1
1 DIMM
-
;
- - - -
2 DIMMs
-
;
-
;
- -
3 DIMMs
-
;
-
;
-
;
4 DIMMs
;
;
-
;
-
;
6 DIMMs
;
;
;
;
;
;
With two processors installed, the system will operate if only the DIMM slots of one processor
are populated. In this case, memory is shared between the two processors. However, due to the
associated latency of this configuration, this is NOT a recommended operating mode.
3.2.1.2
Memory RAS Modes
The server board supports the following memory RAS Modes:
Independent Channel Mode
Mirrored Channel Mode
Mirrored Channel Mode requires that all installed DIMMs support ECC and that there be
matching DIMM populations between channels. Matching DIMMs must meet the following
criteria: DIMM size, DIMM organization (rank, banks, rows, columns). DIMM timings do not have
to match, however, timings will be set to support all DIMMs populated.
Independent channel mode is the only memory RAS mode that supports either non-ECC or
ECC DIMMs.
Independent Channel Mode
In the Channel Independent mode, channels can be populated in any order (e.g., channels B
and C can be populated while channel A is empty). All three channels may be populated in any
order and have no matching requirements. All channels must run at the same interface
frequency, but individual channels may run at different DIMM timings (RAS latency, CAS
latency, and so on).
The single channel mode is established using the Channel Independent mode by populating
DIMM slots from channel A only.