Intel Itanium 9150M, Руководство пользователя

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3:30 Volume 3: Instruction Reference
brl
brl — Branch Long
Format: (
qp
) brl.
btype
.
bwh
.
ph
.
dh target
64
X3
(
qp
) brl.
btype
.
bwh
.
ph
.
dh b
1
=
target
64
call_form X4
brl.
ph
.
dh target
64
pseudo-op
Description:
A branch condition is evaluated, and either a branch is taken, or execution continues
with the next sequential instruction. The execution of a branch logically follows the
execution of all previous non-branch instructions in the same instruction group. On a
taken branch, execution begins at slot 0.
Long branches are always IP-relative. The
target
64
operand, in assembly, specifies a label
to branch to. This is encoded in the long branch instruction as an immediate
displacement (
imm
60
) between the target bundle and the bundle containing this
instruction (
imm
60
=
target
64
- IP >> 4). The L slot of the bundle contains 39 bits of
imm
60
.
There is a pseudo-op for long unconditional branches, encoded like a conditional branch
(
btype
= cond), with the
qp
field specifying PR 0, and with the
bwh
hint of sptk.
The branch type determines how the branch condition is calculated and whether the
branch has other effects (such as writing a link register). For all long branch types, the
branch condition is simply the value of the specified predicate register:
• cond: If the qualifying predicate is 1, the branch is taken. Otherwise it is not taken.
• call: If the qualifying predicate is 1, the branch is taken and several other actions
occur:
• The current values of the Current Frame Marker (CFM), the EC application
register and the current privilege level are saved in the Previous Function State
application register.
• The caller’s stack frame is effectively saved and the callee is provided with a
frame containing only the caller’s output region.
• The rotation rename base registers in the CFM are reset to 0.
• A return link value is placed in BR
b
1
.
Read after Write (RAW) and Write after Read (WAR) dependency requirements for long
branch instructions are slightly different than for other instructions but are the same as
for branch instructions. See
page 3:24 for details.
This instruction must be immediately followed by a stop; otherwise its behavior is
undefined.
Values for various branch hint completers are the same as for branch instructions.
Whether Prediction Strategy hints are shown in
Table 2-7 on page 3:25 , Sequential
Prefetch hints are shown in Table 2-8 on page 3:25 , and Branch Cache Deallocation
hints are shown in Table 2-9 on page 3:25 . See Section 4.5.2, “Branch Prediction Hints”
on page 1:78 .
This instruction is not implemented on the Itanium processor, which takes an Illegal
Operation fault whenever a long branch instruction is encountered, regardless of
whether the branch is taken or not. To support the Itanium processor, the operating
Table 2-10. Long Branch Types
btype Function Branch Condition Target Address
cond or none Conditional branch Qualifying predicate IP-relative
call Conditional procedure call Qualifying predicate IP-relative