Intel Itanium 9150M, Руководство пользователя, Страница: 164 / 420

Volume 3: Instruction Reference 3:155
ld
val = mem_read(paddr, size, UM.be, mattr, otype,
bias | ldhint );
}
}
}
if (check_clear || advanced)
// remove any old ALAT entry
alat_inval_single_entry(GENERAL, r
1
);
if (defer) {
if (speculative) {
GR[ r
1
] = natd_gr_read(paddr, size, UM.be, mattr, otype,
bias | ldhint );
GR[ r
1
].nat = 1;
} else {
GR[ r
1
] = 0; // ld.a to sequential memory
GR[ r
1
].nat = 0;
}
} else { // execute load normally
if (fill_form) { // fill NaT on ld8.fill
bit_pos = GR[ r
3
]{8:3};
GR[ r
1
] = val;
GR[ r
1
].nat = AR[UNAT]{bit_pos};
} else { // clear NaT on other types
if (size == 16) {
GR[ r
1
] = val;
AR[CSD] = val_ar;
}
else {
GR[ r
1
] = zero_ext(val, size * 8);
}
GR[
r
1
].nat = 0;
}
if ((check_no_clear || advanced) && ma_is_speculative(mattr))
// add entry to ALAT
alat_write( ldtype , GENERAL, r
1
, paddr, size);
}
}
if (imm_base_update_form) { // update base register
GR[ r
3
] = GR[ r
3
] + sign_ext( imm
9
, 9);
GR[ r
3
].nat = GR[ r
3
].nat;
} else if (reg_base_update_form) {
GR[ r
3
] = GR[ r
3
] + tmp_r2;
GR[ r
3
].nat = GR[ r
3
].nat || tmp_r2nat;
}
if ((reg_base_update_form || imm_base_update_form) && !GR[ r
3
].nat)
mem_implicit_prefetch(GR[ r
3
], ldhint | bias, itype);
}