Intel Itanium 9150M, Руководство пользователя

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Volume 3: Instruction Reference 3:151
ld
ld — Load
Format: (
qp
) ld
sz
.
ldtype
.
ldhint r
1
= [
r
3
] no_base_update_form M2
(
qp
) ld
sz
.
ldtype
.
ldhint r
1
= [
r
3
],
r
2
reg_base_update_form M2
(
qp
) ld
sz
.
ldtype
.
ldhint r
1
= [
r
3
],
imm
9
imm_base_update_form M3
(
qp
) ld16.
ldhint r
1
, ar.csd = [
r
3
] sixteen_byte_form, no_base_update_form M2
(
qp
) ld16.acq.
ldhint r
1
, ar.csd = [
r
3
] sixteen_byte_form, acquire_form,
no_base_update_form M2
(
qp
) ld8.fill.
ldhint r
1
= [
r
3
] fill_form, no_base_update_form M2
(
qp
) ld8.fill.
ldhint r
1
= [
r
3
],
r
2
fill_form, reg_base_update_form M2
(
qp
) ld8.fill.
ldhint r
1
= [
r
3
],
imm
9
fill_form, imm_base_update_form M3
Description:
A value consisting of
sz
bytes is read from memory starting at the address specified by
the value in GR
r
3
. The value is then zero extended and placed in GR
r
1
. The values of
the
sz
completer are given in Table 2-32 . The NaT bit corresponding to GR
r
1
is cleared,
except as described below for speculative loads. The
ldtype
completer specifies special
load operations, which are described in Table 2-33 .
For the sixteen_byte_form, two 8-byte values are loaded as a single, 16-byte memory
read. The value at the lowest address is placed in GR
r
1
, and the value at the highest
address is placed in the Compare and Store Data application register (AR[CSD]). The
only load types supported for this sixteen_byte_form are
none
and
acq
.
For the fill_form, an 8-byte value is loaded, and a bit in the UNAT application register is
copied into the target register NaT bit. This instruction is used for reloading a spilled
register/NaT pair. See
Section 4.4.4, “Control Speculation” on page 1:60 for details.
In the base update forms, the value in GR
r
3
is added to either a signed immediate
value (
imm
9
) or a value from GR
r
2
, and the result is placed back in GR
r
3
. This base
register update is done after the load, and does not affect the load address. In the
reg_base_update_form, if the NaT bit corresponding to GR
r
2
is set, then the NaT bit
corresponding to GR
r
3
is set and no fault is raised. Base register update is not
supported for the
ld16
instruction.
Table 2-32. sz Completers
sz Completer Bytes Accessed
1 1 byte
2 2 bytes
4 4 bytes
8 8 bytes
Table 2-33. Load Types
ldtype
Completer
Interpretation Special Load Operation
none Normal load
s Speculative load Certain exceptions may be deferred rather than generating a fault.
Deferral causes the target register’s NaT bit to be set. The NaT bit is
later used to detect deferral.
a Advanced load An entry is added to the ALAT. This allows later instructions to check for
colliding stores. If the referenced data page has a non-speculative
attribute, the target register and NaT bit is cleared, and the processor
ensures that no ALAT entry exists for the target register. The absence of
an ALAT entry is later used to detect deferral or collision.