Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset Development Kit
January 2007
User’s Manual
Order Number: 316068-001US
55
Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset
Development Kit
J3A1
5V AUX switch @ 1.7A
1-2: Enable
Open: Disable
1-2
J3D1
Front panel sleep button
Open: (For external access only)
Open
J3J1
For validation only
Open
J3J2
For validation only
Open
J4G1
For validation only
Open
J4G4
For validation only
Open
J4G5
For validation only
Open
J4H1
PCI SMB Clock and PCI SMB Data ground
1-2: SMBData grounded
2-3: SMBClk grounded
Open: IDLE
Open
J5H1
LAN SMB Clock and LAN SMB Data ground
1-2: SMBData grounded
2-3: SMBClk grounded
Open: IDLE
Open
J5H3
DIMM SMB Clock and DIMM SMB Data ground
1-2: SMBData grounded
2-3: SMBClk grounded
Open: IDLE
Open
J4H3
For validation only
Open
J4J1
For validation only
Open
J5A1
To manually control LAN_AUXPWR_STRAP either
pulled up to 3.3V or pulled down to GND
1-2: Disable
2-3: Enable
Open: IDLE
Open
J5D3
MCH SMB Clock and MCH SMB Data ground
1-2: SMBData grounded
2-3: SMBClk grounded
Open: IDLE
Open
J5F1
Enable A16 ICH swap override
Short: Top Swap
Open: Normal
Open
J5F3
Enable ICH run at safe mode
Short: Safe Mode
Open: Normal
Open
J5F5
For validation only
Open
Table 19. Jumpers and Descriptions
Jumper
Description / Settings
Default Position