Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset
Development Kit
Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset Development Kit
User’s Manual
January 2007
54
Order Number: 316068-001US
6.4
Jumpers
The evaluation board has a number of jumpers that control various functions of the
system.
Table 19
presents the descriptions of the jumpers and their settings.
Figure 22
illustrates the locations of key jumpers on the board.
Table 19. Jumpers and Descriptions
Jumper
Description / Settings
Default Position
J2G3
Enable PXH
1-2: Enable (LH)
Open: Disable (LH-VS)
1-2
J2H2
Processor socket occupy signal routing
Short: Processor present
Open: Processor not present
1-2
J2J1
Enable Super IO chip
1-2: Enable
Open: Disable
1-2
J5H2
CMOS clear
1-2: Normal
2-3: Configure
1-2
J7J2
Processor VID override
1-2: Manual select
Open: Processor select
Open
J8H3
Processor VID
VID[5]: 11-12
VID[4]: 1-2
VID[3]: 3-4
VID[2]: 5-6
VID[1]: 7-8
VID[0]: 9-10
(1.212 V)
1-2 Open
3-4 Open
5-6 Short
7-8 Open
9-10 Open
11-12 Short
J4A1
Enable on-board video
1-2: Enable
Open: Disable
1-2
J4H2 (BSEL1), J4J2
(BSEL0)
FSB clock frequency override (J4H2/J4J2/Speed)
Open/Open/166 MHz
1-2/1-2/Auto
J4H2: 1-2
J4J2: 1-2
J5F6 (PLLSEL1), J5E3
(PLLSEL0)
DIMM speed configuration (J5F6/J5E3/FSB Freq)
Open/Short/667
Open/Short/533
J5E3: 1-2
J5F6: Open
J9G4 (DIMCH), J9G3
(MCH_2)
ITP Processor access (J9G3/J9G4/Mode)
1-2/Open/Processor Access Only
2-3/1-2/Chain Test
J9G3: 1-2
J9G4: Open
J1A1
3.3V AUX switch @ 1.7A
1-2: Enable AUX voltage
Open: Disable
1-2
J2G1
For validation only
Open
J2H1
Speaker pull-up routing
1-2: Enable
Open: Disable
Open