Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset
Development Kit
Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset Development Kit
User’s Manual
January 2007
56
Order Number: 316068-001US
J5A1 (3.3V Supply), J5A2
(LAN_AUXPWR_STRAP),
J6B1 (ICH_Wake)
LAN Wake On Control (J5A1/J5A2/J6B1/Lan Wake On
Status)
1-2/1-2/1-2/Wake On
2-3/2-3/1-2/No Wake On
J5A1: 2-3
J5A2: 2-3
J6B1: 1-2
J8H2
DDR S3 Enable BCKFD_CT_LTCH
Short: Enable DIMM S3
Open: Disable DIMM S3
1-2
J7J2
Processor ThermDA and ThermDC External connection
2: Thermal DA connection
3: Ground
Open
Figure 22. Key Jumper Locations
Table 19. Jumpers and Descriptions
Jumper
Description / Settings
Default Position
J9G3/J9G4
J5H2
J8H3
J1A1
J3A1
J8H2
J5E3/J5F6
J4H2/J4J2
J2G3
J2J1
J4A1
J9G3/J9G4
J5H2
J8H3
J1A1
J3A1
J8H2
J5E3/J5F6
J4H2/J4J2
J2G3
J2J1
J4A1