Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset
Development Kit
Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset Development Kit
User’s Manual
January 2007
28
Order Number: 316068-001US
• PCI 2.2 Interface
• Two serial I/O ports
• Two-stage WDT (Watch Dog Timer)
• LPC Interface
• EPLD for Port 80 decode and display
• FWH Interface
• SMBus 2.0 controller
• I/O APIC
• Four USB 2.0 Ports
3.3.5
Intel
®
6700PXH PCI Hub
The 6700PXH provides a connection between the E7520 and PCI or PCI-X interfaces via
a PCIe channel. The 6700PXH PCI Hub contains two PCI bus interfaces that have been
configured to PCI-X 133 MHz and the other to PCI-X 100 MHz, for either 32-bit or 64-
bit PCI devices.
• Two PCI-X 100 MHz slots
• One PCI-X 133 MHz slot
3.3.6
Intel
®
82571EB Gigabit Ethernet Controller
The Intel 82571EB Gigabit Ethernet Controller is a single, compact component with two
fully integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY)
ports. Uses the PCI Express X4 connection to the Intel
®
E7520 MCH. The Intel
82571EB provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-
TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). In addition to managing
MAC and PHY Ethernet layer functions, the controller manages PCI Express packet
traffic across its transaction, link, and physical/logical layers.
3.3.7
Memory Subsystem
The memory subsystem is designed to support Double Data Rate 2 (DDR2)
Synchronous Dynamic Random Access Memory (SDRAM) using the Intel
®
E7520 MCH.
The MCH provides two independent DDR channels, which support DDR2-400 DIMMs.
The peak bandwidth of each DDR2 branch channel is 3.2 GByte/s (8 bytes x 400 MT/s)
with DDR2-400. When the two DDR2 channels from the MCH operate in lock step, the
effective overall peak bandwidth of the DDR2 memory subsystem is 6.4 GByte/s for
DDR2-400.
