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5 Troubleshooting
5
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E3.102: Abnormal communication initialization of coprocessor
Cause:
Multi-core communication initialization fault or software version of cores not matching
Probable Cause
Confirming Method
Corrective Action
1. The FPGA software
version and the
software version of
CPU cores do not
match.
View the FPGA software version (2001-03h) and the
CUP0 software version (2001-04h) and the CUP1 software
version (2001-05h) via the keypad or the Inovance servo
commissioning software. Check whether the non-zero
value of the most significant bit is the same in the two
versions.
Contact Inovance for
technical support. Update
the software to make them
match.
2. The FPGA is faulty.
The fault persists after the servo drive is powered off and
on for several times.
Replace the servo drive.
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E3.104: Abnormal communication or interrupt timeout of coprocessor
Cause:
Coprocessor or FPGA interrupt timeout, cyclic access among coprocessors timeout
Probable Cause
Confirming Method
Corrective Action
1. The FPGA is faulty.
The fault persists after the servo drive
is powered off and on several times.
Replace the servo drive.
2.
The communication handshake between
the FPGA and the MCU is abnormal.
3. MCU interrupt times out.
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E3.105: Internal program abnormal
Cause:
The total number of parameters is abnormal at EEPROM reading/writing operation.
The data range of parameters is abnormal, which generally occurs after software updates.
Probable Cause
Confirming Method
Corrective Action
1. An EEPROM fault occurs.
Check the causes according to the
method of E3.101.
Restore the default setting (2002-
20h=1), and power on the system
again.
2. The servo drive is faulty.
The fault persists after the servo drive is
powered off and on several times.
Replace the servo drive.
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E3.106: abnormal communication of the main processor
To distinguish the fault symptom, the servo drive displays different internal fault codes under the same fault
code. You can view these internal fault codes in 200B-2Eh.
Cause:
Access between HOST and FPGA or between Host and coprocessor times out during power-on initialization.
Probable Cause
Confirming Method
Corrective Action
1. The FPGA is faulty.
The fault persists after the servo drive
is powered off and on several times.
Replace the servo drive.
2.
The communication handshake between
the FPGA and the HOST is abnormal.
3. Access between HOST and coprocessor
times out.
Содержание SV820N Series
Страница 127: ...126 6 Trial Running 6 6 5 6 PLC Program 1 Add an FB file that edits the function block in the application...
Страница 128: ...127 6 Trial Running 6 2 The definition part of FB 3 Five function blocks in FB...
Страница 141: ...140 6 Trial Running 6 In section0 call the function block then the axis can be moved by the bus...
Страница 143: ...142 6 Trial Running 6 3 Open Visual studio and create a New Twincat3 Project...
Страница 146: ...145 6 Trial Running 6 Click OK Click OK...
Страница 147: ...146 6 Trial Running 6 Click Yes Click OK...
Страница 149: ...148 6 Trial Running 6 C The default RPDO list is as follows...
Страница 150: ...149 6 Trial Running 6...
Страница 152: ...151 6 Trial Running 6 7 Activate the configuration and switch over to the running mode Click...
Страница 157: ...156 6 Trial Running 6 Add a motion control library making it easy to call the control function block...
Страница 158: ...157 6 Trial Running 6 Create a new POU...
Страница 159: ...158 6 Trial Running 6 Create a new FB add MC_power MC_jog MC_home MC_absolute MC_reset to FB...
Страница 160: ...159 6 Trial Running 6 Call axis_motion in main Call the program in PLCTASK...
Страница 161: ...160 6 Trial Running 6 Compile the program if there is no fault configuration can be activated and then log in to the PLC...
Страница 181: ...Revision History Date Revised Version Revised Details May 2017 A00 First release...