IDT PCI Express 89HPES32NT24xG2, Руководство пользователя, Страница: 57 / 744

Notes
PES32NT24xG2 User Manual 2 - 1 January 30, 2013
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Chapter 2
Clocking
Overview
Figure 2.1 provides a logical representation of the PES32NT24xG2 clocking architecture. The switch
has two differential global reference clock input (GCLK) pairs as well as several differential reference clock
inputs (PxCLK) used for local port clocking.
The differential global reference clock input (GCLK) is driven into the device on the GCLKP[1:0] and
GCLKN[1:0] pins. The nominal frequency of the global reference clock input may be selected by the Global
Clock Frequency Select (GCLKFSEL) pin to be either 100 MHz or 125 MHz (+/- 300 ppm). Both global
reference clock differential inputs should be driven with the same frequency. However, there are no skew
requirements between the GCLKP[0]/GCLKN[0] and GCLKP[1]/GCLKN[1] inputs. Any constant phase
difference is acceptable.
The global reference clock input is provided to each SerDes quad and to an on-chip PLL. The on-chip
PLL uses this clock to generate a 250 MHz core clock that is used by internal switch logic (e.g., switch core,
portion of a stack, etc.). The PLL within each SerDes quad generates a 5.0 GHz clock used by the SerDes
analog portion (PMA) and a 250 MHz clock used by the digital portion (PCS).
Associated with some ports is a port reference clock input (PxCLK). Depending on the port clocking
mode (see section Port Clocking Modes on page 2-2), a differential reference clock is driven into the device
on the corresponding PxCLKP and PxCLKN pins.
Note: The nominal frequency of a port reference clock input (PxCLK) is 100 MHz (+/- 300 ppm),
except in cases where the restrictions outlined in section Port Clocking Mode Selection on page 2-6
apply. The PxCLK supports SSC as described in section Support for Spread Spectrum Clocking
(SSC) on page 2-5.
There are no skew requirements between the global clock input and a port reference clock input or
between any of the port reference clock inputs. Any constant phase difference is acceptable.
The clocking architecture for the PES32NT24AG2 device is shown in Figure 2.1. This device has a port
clock for each of the 8 ports. The clocking architecture for the PES32NT24BG2 device is shown in Figure
2.2. The “B” device supports on 3 port clocks (Ports 0, 2, and 4).