IDT 89HPES12T3G2, Предварительное руководство пользователя

Страница: 31 / 146

IDT Clocking, Reset and Initialization
PES12T3G2 User Manual 2 - 3 January 28, 2013
Notes
Fundamental Reset
A Fundamental Reset may be initiated by any of the following conditions:
– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input
pin.
– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power
is on.
– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch
Control (SWCTL) register.
When configured to operate in normal mode, the following reset sequence is executed.
1. Wait for the Fundamental Reset condition to clear (e.g., negation of PERSTN). Note that PERSTN
must be asserted for at least 100 ms (Tpvperl) after the PES12T3G2 power supplies are stable, and
100µ s (Tperst-clk) after the reference clock input is stable.
2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.2. If PERSTN was
not asserted, use the previously sampled boot configuration signal values (e.g., when a Funda-
mental Reset is the result of setting the Fundamental Reset (FRST) bit in the Switch Control
(SWCTL) register).
• Examine the state of the sampled SWMODE[2:0] signals to determine the switch operating
mode.
3. The PLL and SerDes are initialized (i.e., PLL/CDR reset and lock).
4. Link training begins. While link training is in progress, proceed to step 5.
5. If the Reset Halt (RSTHALT) pin is asserted, the RSTHALT bit in the SWSTS register is set.
6. If the switch operating mode is not a test mode, then the reset signal to the PCI Express stacks and
associated logic is negated but they are held in a quasi-reset state in which the following actions
occur.
• All links enter an active link training state within 20 ms of the clearing of the Fundamental Reset
condition.
• Within 100 ms of the clearing of the Fundamental Reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration
request retry status completion. All other transactions are ignored.
7. The master SMBus operating frequency is determined.
• The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is
initialized to operate at 100 KHz rather than 400 KHz.
8. The slave SMBus is taken out of reset and initialized. The slave SMBus address specified by the
SSMBADDR[5,3:1] pins is used.
9. The master SMBus is taken out of reset and initialized.
10. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then
the contents of the serial EEPROM are read and the appropriate PES12T3G2 registers are updated.
• If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link
State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using
the current link parameters.
• If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in
the SMBUSSTS register.
• When serial EEPROM initialization completes or when an error is detected, the EEPROM Done
(EEPROMDONE) bit in the SMBUSSTS register is set.
• If the RSTHALT bit is set in the SWCTL register, proceed to step 11. Else, proceed to step 12.
11. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state
except the master and slave SMBuses, the control/status registers, and the stacks which continue
to be held in a quasi-reset state and respond to configuration transactions with a retry. The device