IDT 89HPES12T3G2, Предварительное руководство пользователя

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IDT Hot-Plug and Hot-Swap
PES12T3G2 User Manual 7 - 4 January 28, 2013
Notes
(EIS) bit in the PCI Express Slot Status (PCIESSTS) register. In this mode the state of the Manually-oper-
ated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the
RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of corre-
sponding PxILOCKP I/O expander signal output.
When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the
Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register,
then power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This
occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control
(PCIESCTL) register.
The state of a port’s Power Fault (PxPFN) input is not latched by the PES12T3G2. For proper operation
the system designer should ensure that once the PxPFN signal is asserted, it remains asserted until the
power enable (PxPEP) signal is toggled. This is required adapter behavior for the PCI Express Express-
Module form factor. Downstream port reset outputs are described in section Downstream Port Reset
Outputs on page 2-7 .
The default value of hot-plug registers following a Hot-Reset or Fundamental Reset may be configured
via serial EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM
initialization, the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS)
register as a result of serial EEPROM initialization.
Hot-Plug I/O Expander
The PES12T3G2 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus inter-
face for hot-plug related signals associated with downstream ports. See section I/O Expanders on page 5-6
for details on the operation of the I/O expanders and for the mapping of downstream hot-plug signals to I/O
expander inputs and outputs.
Hot-Plug Interrupts and Wake-up
The hot-plug controller associated with a downstream slot may generate an interrupt or wake-up event.
Hot-plug interrupts are only generated when the Hot Plug Interrupt Enable (HPIE) bit is set in the corre-
sponding port’s PCI Express Slot Control (PCIESCTL) register.
The following bits, when set in the PCI Express Slot Status (PCIESSTS) register, generate an interrupt if
not masked by the corresponding bit in the PCI Express Slot Control (PCIESCTL) register or by the HPIE
bit: the Attention Button Pressed (ABP), Power Fault Detected (PFD), MRL Sensor Changed (MRLSC),
Presence Detected Changed (PDC), and Command Completed (CC).
When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable
(EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command
(PCICMD) register. When the downstream port or the entire switch is in a D3
hot
state, the hot-plug controller
generates a wake-up event using a PM_PME message instead of an interrupt if the event interrupt is not
masked in the slot control (PCIESCTL) register and hot-plug interrupts are disabled by the HPIE bit. If the
event interrupt is not masked and hot-plug interrupts are enabled, both a PM_PME and an interrupt are
generated. If the event interrupt is masked, neither a PM_PME nor an interrupt is generated. Note that a
command completed (CC bit) interrupt will not generate a wakeup event.
Legacy System Hot-Plug Support
Some systems require support for operating systems that lack PCIe hot-plug support. The PES12T3G2
supports these systems by providing a General Purpose Event (GPEN) output as an alternate function of
GPIO[7] that can be used instead of the INTx, MSI, and PME mechanisms defined by PCI Express hot-
plug.
Associated with each downstream port’s hot-plug controller is a bit in the General Purpose Event
Control (P0_GPECTL) register. When this bit is set, the corresponding PCIe base 2.0 hot plug event notifi-
cation mechanisms are disabled for that port and INTx, MSI, and PME events will not be generated by that
port due to hot-plug events. Instead, hot-plug events are signaled through assertion of the GPEN signal.