IDT 89HPES12T3G2, Предварительное руководство пользователя

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IDT Configuration Registers
PES12T3G2 User Manual 8 - 25 January 28, 2013
Notes
5 LRET RW 0x0 Link Retrain. Writing a one to this field initiates Link retraining
by directing the Physical Layer LTSSM to the Recovery state.
This field always returns zero when read.
It is permitted to set this bit while simultaneously modifying
other fields in this register.
When this bit is set and the LTSSM is already in the Recovery
or Configuration states, all modifications that affect link retrain-
ing are applied in the subsequent retraining. Else, if the LTSSM
is not in the Recovery or Configuration states, modifications
that affect link retraining are applied immediately.
For compliance with the PCIe specification, this bit has no
effect on the upstream port when the REGUNLOCK bit is
cleared in the SWCTL register. In this mode the field is hard-
wired to zero. When the REGUNLOCK bit is set, writing a one
to the LRET bit initiates link retraining on the upstream port with
a delayed effect of 1 ms. The PES12T3G2 always returns a
completion to the requester before the effect of this bit is
applied.
6 CCLK RW 0x0 Common Clock Configuration. When set, this bit indicates
that this component and the component at the opposite end of
the link are operating with a distributed common reference
clock.
7 ESYNC RW 0x0 Extended Sync. When set this bit forces transmission of addi-
tional ordered sets when exiting the L0s state and when in the
recovery state.
8 CLKPWRMGT RO 0x0 Enable Clock Power Management. The PES12T3G2 does
not support this feature.
9 HAWD RO 0x0 Hardware Autonomous Width Disable. When set, this bit dis-
ables hardware from changing the link width for reasons other
than attempting to correct for unreliable link operation by reduc-
ing the link width.
The PES12T3G2 ports do not have a hardware autonomous
mechanism to change link width, except due to link reliability
issues. Therefore, this bit is not applicable to the PES12T3G2
ports.
Note that this bit does not affect link width changes triggered by
the link width re-configuration mechanism.
10 LBWINTEN RW 0x0 Link Bandwidth Management Interrupt Enable. When set,
this bit enables the generation of an interrupt to indicate that
the LBWSTS bit has been set in the PCIELSTS register.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in the upstream port.
11 LABWINTEN RW 0x0 Link Autonomous Bandwidth Interrupt Enable. When set,
this bit enables the generation of an interrupt to indicate that
the LABWSTS bit has been set in the PCIELSTS register.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in the upstream port.
15:12 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description