Notes
PES12T3G2 User Manual
3 - 1
January 28, 2013
®
Chapter 3
Link Operation
Introduction
Link operation in the PES12T3G2 adheres to the PCI Express 2.0 Base Specification, supporting
speeds of 2.5 Gbps and 5.0 Gbps. The PES12T3G2 contains four ports. All ports operate with a maximum
link width of x4. The SerDes lanes are statically assigned to a port.
Polarity Inversion
Each port of the PES12T3G2 supports automatic polarity inversion as required by the PCIe specifica-
tion. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its
data. During link training, the receiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for
inversion of the PExRP[n] and PExRN[n] signals. If an inversion is detected, then logic for the receiving
lane automatically inverts received data. Polarity inversion is a lane and not a link function. Therefore, it is
possible for some lanes of link to be inverted and for others not to be inverted.
Lane Reversal
The PCIe specification describes an optional lane reversal feature. The PES12T3G2 supports the auto-
matic lane reversal feature outlined in the PCIe specification. The operation of lane reversal is dependent
on the maximum link width selected by the MAXLNKWDTH field in the PCI Express Link Capabilities
(PCIELCAP) register. Lane reversal mapping for the various non-trivial x4 port maximum link width configu-
rations supported by the PES12T3G2 are illustrated in Figures 3.1 and 3.2.
Figure 3.1 Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH=0x4)
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 0
lane 1
lane 2
lane 3
(a) x4 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 3
lane 2
lane 1
lane 0
(b) x4 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 0
lane 1
(a) x2 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 1
lane 0
(b) x2 Port with lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 0
(a) x1 Port without lane reversal
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PES12T3G2
lane 0
(b) x1 Port with lane reversal
Содержание 89HPES12T3G2
Страница 10: ...IDT Table of Contents PES12T3G2 User Manual iv January 28 2013 Notes...
Страница 12: ...IDT List of Tables PES12T3G2 User Manual vi January 28 2013 Notes...
Страница 14: ...IDT List of Figures PES12T3G2 User Manual viii January 28 2013 Notes...
Страница 18: ...IDT Register List PES12T3G2 User Manual xii January 28 2013 Notes...
Страница 46: ...IDT Link Operation PES12T3G2 User Manual 3 10 January 28 2013 Notes...
Страница 66: ...IDT SMBus Interfaces PES12T3G2 User Manual 5 18 January 28 2013 Notes...
Страница 70: ...IDT Power Management PES12T3G2 User Manual 6 4 January 28 2013 Notes...
Страница 138: ...IDT Configuration Registers PES12T3G2 User Manual 8 62 January 28 2013 Notes...