IDT Configuration Registers
PES12T3G2 User Manual
8 - 44
January 28, 2013
Notes
AERCEM - AER Correctable Error Mask (0x114)
Bit
Field
Field
Name
Type Default
Value
Description
0
RCVERR
RW
0x0
Sticky
Receiver Error Mask. When this bit is set, the corresponding bit in
the AERCES register is masked. When a bit is masked in the
AERCES register, the corresponding event is not reported to the
root complex.
5:1
Reserved
RO
0x0
Reserved field.
6
BADTLP
RW
0x0
Sticky
Bad TLP Mask. When this bit is set, the corresponding bit in the
AERCES register is masked. When a bit is masked in the AERCES
register, the corresponding event is not reported to the root com-
plex.
7
BADDLLP
RW
0x0
Sticky
Bad DLLP Mask. When this bit is set, the corresponding bit in the
AERCES register is masked. When a bit is masked in the AERCES
register, the corresponding event is not reported to the root com-
plex.
8
RPLYROVR
RW
0x0
Sticky
Replay Number Rollover Mask. When this bit is set, the corre-
sponding bit in the AERCES register is masked. When a bit is
masked in the AERCES register, the corresponding event is not
reported to the root complex.
11:9
Reserved
RO
0x0
Reserved field.
12
RPLYTO
RW
0x0
Sticky
Replay Timer Time-Out Mask. When this bit is set, the corre-
sponding bit in the AERCES register is masked. When a bit is
masked in the AERCES register, the corresponding event is not
reported to the root complex.
13
ADVISO-
RYNF
RW
0x1
Sticky
Advisory Non-Fatal Error Mask.When this bit is set, the corre-
sponding bit in the AERCES register is masked. When a bit is
masked in the AERCES register, the corresponding event is not
reported to the root complex.
31:14
Reserved
RO
0x0
Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
4:0
FEPTR
RO
0x0
Sticky
First Error Pointer. This field contains a pointer to the bit in the
AERUES register that resulted in the first reported error.
5
ECRCGC
RWL
0x1
ECRC Generation Capable. This bit indicates if the device is capa-
ble of generating ECRC.
6
ECRCGE
RW
0x0
Sticky
ECRC Generation Enable. When this bit is set, ECRC generation
is enabled.
7
ECRCCC
RWL
0x1
ECRC Check Capable. This bit indicates if the device is capable of
checking ECRC.
8
ECRCCE
RW
0x0
Sticky
ECRC Check Enable. When set, this bit enables ECRC checking.
31:9
Reserved
RO
0x0
Reserved field.
Содержание 89HPES12T3G2
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