IDT 89HPES12T3G2, Предварительное руководство пользователя

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Notes
PES12T3G2 User Manual 2 - 1 January 28, 2013
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Chapter 2
Clocking, Reset and
Initialization
Clocking
The PES12T3G2 has a single differential reference clock input (PEREFCLKP[0]/PEREFCLKN[0]) that is
used internally to generate all of the clocks required by the internal switch logic and the SerDes. The
frequency of the reference clock inputs may be selected by the Reference Clock Mode Select (REFCLKM)
input (see Table 2.1). All reference clock inputs must have the same frequency, as selected by REFCLKM.
Each PES12T3G2 port has an associated PLL. The reference clock differential inputs feed the on-chip
PLLs (one PLL per SerDes quad). Each PLL generates a 5.0 GHz internal SerDes clock which is used by
the four SerDes lanes in a SerDes quad. The PLL also produces a 250 MHz core clock, named PCLK. The
250 MHz PCLK output from the upstream port (i.e., Port 0) is used as the system clock for internal switch
logic. When the switch is placed in PLL Bypass test mode via the SWMODE pins, the 250 MHz clock gener-
ated by the PLL is bypassed and the reference clock input on PEREFCLKP[0]/PEREFCLKN[0] is used for
the core logic.
Initialization
A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES12T3G2
during a Fundamental Reset when PERSTN is negated. The boot configuration vector defines essential
parameters for switch operation.
Since the boot configuration vector is sampled only during a Fundamental Reset sequence, the value of
signals which make up the boot configuration vector is ignored during other times and their state outside of
a Fundamental Reset has no effect on the operation of the PES12T3G2. While basic switch operation may
be configured using signals in the boot configuration vector, advanced switch features require configuration
via an external serial EEPROM. The external serial EEPROM allows modification of any bit in any software
visible register. See Chapter 5, SMBus Interfaces, for more information on the serial EEPROM.
The external serial EEPROM and slave SMBus interface may be used to override the function of some
of the signals in the boot configuration vector during a Fundamental Reset. The signals that may be over-
ridden are noted in Table 2.2. The state of all of the boot configuration signals in Table 2.2 sampled during
the most recent Fundamental Reset may be determined by reading the SWSTS register.
REFCLKM Description
0 100 MHz reference clock input.
1 125 MHz reference clock input.
Table 2.1 Reference Clock Mode Encoding