HPE ProLiant SL270s Gen8, Руководство пользователя

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Hardware options installation 31
while the industry supports DDR3-1333 RDIMM at 1.5V, this Gen8 server supports DDR3-1333 RDIMM
at 1.35V. This difference equates to up to 20% less power at the DIMM level with no performance penalty.
Memory subsystem architecture
The memory subsystem in this server is divided into channels. Each processor supports four channels,
and each channel supports two DIMM slots, as shown in the following table.
Channel Slot Slot number
1
A
E
1
2
2
B
F
3
4
3
C
G
8
7
4
D
H
6
5
For the location of the slot numbers, see "DIMM slot locations (on page 10 )."
This multi-channel architecture provides enhanced performance in Advanced ECC mode. This
architecture also enables the Lockstep memory mode.
DIMM slots in this server are identified by number and by letter. Letters identify the population order. Slot
numbers indicate the DIMM slot ID for spare replacement.
Single-, dual-, and quad-rank DIMMs
To understand and configure memory protection modes properly, an understanding of single-, dual-, and
quad-rank DIMMs is helpful. Some DIMM configuration requirements are based on these classifications.
A single-rank DIMM has one set of memory chips that is accessed while writing to or reading from the
memory. A dual-rank DIMM is similar to having two single-rank DIMMs on the same module, with only one
rank accessible at a time. A quad-rank DIMM is, effectively, two dual-rank DIMMs on the same module.
Only one rank is accessible at a time. The server memory control subsystem selects the proper rank
within the DIMM when writing to or reading from the DIMM.
Dual- and quad-rank DIMMs provide the greatest capacity with the existing memory technology. For
example, if current DRAM technology supports 8-GB single-rank DIMMs, a dual-rank DIMM would be 16
GB, and a quad-rank DIMM would be 32 GB.
LRDIMMs are labeled as quad-rank DIMMs; however, they function more like dual-rank DIMMs. There
are four ranks of DRAM on the DIMM, but the LRDIMM buffer creates an abstraction that allows the DIMM
to appear as a dual-rank DIMM to the system. The LRDIMM buffer also isolates the electrical loading of
the DRAM from the system to allow for faster operation. These two changes allow the system to support
up to three LRDIMMs per memory channel, providing for up to 50% greater memory capacity and higher
memory operating speed compared to quad-rank RDIMMs.