HP ESG-D Series, Руководство пользователя

Страница: 658 / 712

7-12
Operation
Frame/Pattern Triggering (Option 1EH)
Frame/Pattern Triggering (Option 1EH)
The PATTERN TRIG IN connector is used to trigger the internal digital
modulation data generator to start a single pattern output or to stop and
re-synchronize a pattern that is being continuously output. The input levels are
TTL.
Triggering a Single Pattern
To trigger a single pattern, the trigger must be sampled low on a data clock rising
edge and then be sampled high on the next, or some later, clock rising edge. The
trigger must remain high until after the pattern ends. If the trigger is high, the
pattern will stop after the last bit. When the trigger makes the next low to high
transition, the pattern is reset to the first bit and re-started.
If the trigger transitions from high to low before the pattern ends, the pattern will
reset to the first bit and re-start at the next low to high trigger transition. If the
PATTERN TRIG IN signal is held high and only pulse it low and then high to
trigger the pattern, the pattern will not be reset due to an inappropriate high to low
trigger transition.
If there is no input to the PATTERN TRIG IN connector, it is internally pulled to a
high state. A single pattern is output once the pattern repeat is set to single. This
allows the signal generator to internally-trigger a single pattern.
In the single pattern mode, when the complete pattern is transmitted, the I and Q
outputs will continue to clock and send phase transitions controlled by the last
symbol data and the symbol sync state in the pattern. If the pattern is reset before
it finishes, the I and Q outputs will continue to clock and send phase transitions
controlled by the first data bit and the symbol sync state in the pattern.
Pattern Trig In
Data Clock
Data
Pattern No
Pattern
Transmission
Transmission Transmission
No
Transmission