HP ESG-D Series, Руководство пользователя

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7-9
Operation
Frame/Pattern Triggering (Options UN3 and UN4)
Example 1
In this example, the timing diagram shows the trigger occurring on time (1.5 to
2.5 bit clocks before the present frame ends) to generate continuous frame timing.
The rising edge of the trigger is shown to occur at any time after the last bit clock
falling edge and before the next bit clock falling edge.
Example 2
In this example, two timing diagrams are shown. In the first, the trigger occurs
late (1.5 to 0.5 bit clocks before the present frame ends). The outcome is an
additional guard bit inserted between the last bit of the present frame and the first
bit of the next frame.
Data Clock
Pattern Trig In
. . . . . .
Data
Last Bit of First Bit of
Frame Frame
Data Clock
Pattern Trig In
. . . . . .
Data
Last Bit of First Bit of
Frame
Frame
+ 1 Bit