HP ESG-D Series, Руководство пользователя

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7-6
Operation
Data Clock Timing Patterns (Options UN3 and UN4)
Data Clock Timing Patterns (Options UN3 and UN4)
GSM and DECT
The diagram shows both the DATA CLOCK INPUT signal and the DATA INPUT
pattern (one bit per symbol). Notice that the data should change (zero to one or
one to zero) on the rising edge of the data clock and the data must be stable on the
falling edge of the data clock.
NADC, PDC, PHS, and TETRA
The following timing diagram shows the following information:
• external DATA CLOCK INPUT signal in normal and symbol modes
• SYMBOL SYNC INPUT signal in continuous and single modes
• symbol bits (2 bits per symbol)
• DATA INPUT pattern
Notice that the data should change (zero to one or one to zero) on the rising edge
of the data clock and the data must be stable on the falling edge of the data clock.
Data Clock
Data
where X is data transition; = is data valid 0 or 1
±
=====X========X========X========X========X=======
Ext Data Clock
Data
where X is data transition; = is data valid 0 or 1
±
=====X========X========X========X========X=======
Normal
Symbol
Symbol Sync
Continuous
Single
Symbol Bit 1
2 1 2