HP 16555A, Руководство по обслуживанию

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To test the multiple-clock, multiple-edge, state acquisition
Testing the multiple-clock, multiple-edge, state acquisition verifies the performance
of the following specifications:
•
Minimum master to master clock time.
•
Maximum state acquisition speed.
•
Setup/Hold time.
•
Minimum clock pulse width.
Multicard modules must be reconfigured as one-card modules for this test.
This test checks a combination of data channels using multiple clocks at three
selected setup/hold times.
Equipment Required
Equipment Critical Specifications Recommended
Model/Part
Pulse Generator 100 MHz 3.5 ns pulse width, <600 ps rise time HP 8131A option 020
Digitizing Oscilloscope
≥
6 GHz bandwidth, <58 ps rise time HP 54750A w/ HP 54751A
Adapter SMA(m)-BNC(f) HP 1250-1200
SMA Coax Cable (Qty 3) HP 8120-4948
Coupler (Qty 3) BNC(m-m) HP 1250-0216
BNC Test Connector, 6x2 (Qty 3)
Set up the equipment
1
Turn on the equipment required and the logic analyzer. Let them warm up for
30 minutes before beginning the test if you have not already done so.
2
Set up the pulse generator according to the following table.
Pulse Generator Setup
Channel 1 Channel 2 Period
Delay: 0 ps Doub: 10.0 ns 20.0 ns
Width: 4.5 ns Width: 3.5 ns
High:
−
0.9 V High:
−
0.9 V
Low:
−
1.7 V Low:
−
1.7 V
COMP: Disabled
(LED off) COMP: Disabled
(LED off)
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