HP 16555A, Руководство по обслуживанию

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Characteristics
The characteristics are not specifications, but are included as additional information.
Full Channel Half Channel *
Maximum State Clock Rate 110 MHz Not applicable
Maximum Conventional Timing Rate 250 MHz 500 MHz
Channel Count per Card 68 34
Channel Count per Three-Card Module 204 102
Memory Depth (HP 16555A) 1016K 2088K
Memory Depth (HP 16555D) 2032K 4177K
* Half channel mode is only available for timing analysis.
Supplemental Characteristics
Probes
Input Resistance 100 k
Ω
,
±
2%
Input Capacitance ~ 8 pF
Minimum Voltage Swing 500 mV, peak-to-peak
Maximum Input Voltage
±
40 V, CAT I
Threshold Range
±
6.0 V, adjustable in 50-mV increments
Clock In/Out
Clock Output 850 mV @100 MHz, terminated into 50
Ω
.
Clock Input 1.0 V @100 MHz,
±
20 Vdc offset (clock input port
is terminated internally to 50
Ω
).
State Analysis
State/Clock Qualifiers 4
Time Tag Resolution
*
8 ns
Maximum Time Count Between States 34 seconds
Maximum State Tag Count
*
4.29 x 10
9
Timing Analysis
Sample Period Accuracy 0.01 % of sample period
Channel-to-Channel Skew 2 ns, typical
Time Interval Accuracy
±
[sample channel-to-channel skew
+(0.01%)(time reading)]
General Information
Characteristics
1–4