2
Using the Delay mode of the pulse generator channel 1, position the pulses
according to the setup/hold combination selected, +0.0 ps or -100 ps.
a
On the Oscilloscope, select [Define meas] Define
∆
Time - Stop edge: rising.
b
In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,
position the falling edge of the data waveform so that it is centered on the display.
c
On the oscilloscope, select [Shift]
∆
Time. Select Start src: channel 1, then select
[Enter] to display the setup time (
∆
Time(1)-(2)).
d
Adjust the pulse generator channel 2 Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
3
Select the clock to be tested.
a
Touch the clock field to be tested and then select the clock as indicated in the table.
The first time through this test, select the top multiple-edge clock.
Clocks
J
↕
K
↕
L
↕
M
↕
b
Touch Done to exit the Master Clock menu.
Testing Performance
To test the single-clock, multiple-edge, state acquisition
3–49
Содержание 16555A
Страница 4: ...The HP 16555A D Logic Analyzer iii ...
Страница 15: ...1 8 ...
Страница 97: ...3 70 ...
Страница 98: ...4 Calibrating ...
Страница 102: ...Troubleshooting Flowchart 1 Troubleshooting To use the flowcharts 5 3 ...
Страница 103: ...Troubleshooting Flowchart 2 Troubleshooting To use the flowcharts 5 4 ...
Страница 104: ...Troubleshooting Flowchart 3 Troubleshooting To use the flowcharts 5 5 ...
Страница 105: ...Troubleshooting Flowchart 4 3 Troubleshooting To use the flowcharts 5 6 ...
Страница 117: ...5 18 ...
Страница 125: ...6 8 ...
Страница 126: ...7 Replaceable Parts Ordering 7 2 Replaceable Parts List 7 3 Exploded View 7 5 Replaceable Parts ...
Страница 130: ...Exploded View Exploded view of the HP 16555A D logic analyzer Replaceable Parts Exploded View 7 5 ...
Страница 131: ...7 6 ...
Страница 132: ...8 Block Level Theory 8 2 Self Tests Description 8 6 Theory of Operation ...