MAN1032-10-EN_EXL6_UserManual
March 12, 2020
105 | 191
The state (high or low) of the high-speed input is sampled with every rising input edge of the
filter frequency. The rising edges of the filter frequency are totaled in a sample counter, and
when that total equals the number of samples configured, the sample counter is reset. If the
high-speed input state did not change by the time of the sample counter reset, that state, high
or low, is passed on to the high-speed accumulator. If the high-speed input state changes during
the sample counting, the sample counter is reset to zero and the process starts over.
Figure 1: Input Signal
Figure 2: Filter Frequency: Example 1MHz
Number of samples: 4
If user selects filter frequency as 1MHz and Number of samples as 4, then Input signal is sampled
for 4 samples and if the signal is stable for 4 samples i.e. 4
μ
s then the signal is passed to
Accumulator.
If the Input state is changed in between the sampling counts, then the count is reset, and the
Input state is again checked for given number of samples.
Refer to Dotted lines in the Figure 2, after 2 samples the state of input signal changes to 1, so
the counter is again started to count 4 samples, to pass the signal to accumulator.
There will be a delay in passing the input signal to accumulator since we are filtering the Input
signal and the delay is based on the selected filter frequency and Number of samples. In the
above example filter frequency is 1MHZ (1
μ
s) and number of samples: 4, so the minimum delay
in input signal will be 4
μ
s.
