5 Configuration Mode Introduction
5.1 Configuration Notes
UG290-2.3E
17(87)
RECONFIG_N can be left floating or externally pulled up. All GPIOs output
high impedance state before FPGA is waken up.
GOWINSEMI FPGA products write bitstream data to SRAM, on-chip
Flash, or off-chip Flash according to the data storage and the instructions.
Only the LittleBee
®
Family of FPGA products support operations on on-chip
Flash. All products support operations on SRAM and external Flash.
SRAM Operation
The SRAM operations include read device ID CODE and USER
CODE, read device status register information and SRAM configuration.
The device ID needs to be verified before configuration. Only the device
with successful ID verification can be configured. The USER CODE is the
identification number for users to distinguish between the devices that
share the same ID CODE. The state register of the device records the
status information before and after FPGA configuration, and you can use
this information to analyze the state of the device accordingly. Please refer
to Table 5-10 for the meaning of the status register. During SRAM
configuration, only the bitstream data with no security bit setting supports
validation. Data with security bit cannot be readback or verified.
On-chip/Off-chip Flash Operation
The built-in flash operations include erasing, programming and
verification. The built-in flash can only be programmed via the JTAG
interface, and the clock rate is no less than 1MHz. Please refer to Table 5-7
for the clock rate.
Note!
During configuring SRAM devices via built-in Flash (AUTOBOOT configuration and
DUALBOOT configuration) and programming built-in Flash, the FPGA needs to remain
powered up, and the RECONFIG_N cannot be triggered at low level; otherwise, it may
cause irreparable damages to the built-in Flash.
It is required to clear the SRAM content before programming the
embedded Flash or external Flash of the A version of LittleBee
®
family
devices. The B version of LittleBee
®
family devices supports the feature of
transparent transmission. That is to say, the B version device can program
the embedded Flash or external Flash via the JTAG interface without
affecting the current working state. During programming, the B version
device works according to the previous configuration. After programming,
RECONFIG_N is triggered at low pulse to complete the online upgrade.
This feature applies to the applications requiring long online time and
irregular upgrades.
Dual-purpose Pin Configuration
In different configuration modes, users need to ensure that FPGA
works in the selected configuration mode according to the pin functions. If
user pins is insufficient, these pins can be configured and used as GPIOs,
but pins associated with data transmission need to be kept. MODE [2:0] is
used to select the GowinCONFIG programming configuration MODE.
MODE can be fixed through pull-up or pull-down resister. It is
recommended to use 4.7 K pull-up resister and1 K pull-down resistor.
