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APPENDIX A: PROGRAMMABLE OSCILLATOR PROGRAMMING
The 4 on-baord clock frequencies are supplies via two Cypress Semiconductor CY22393 Programmable Clock
Generatosr. In order to change the clock frequencies, this chip must be reprogrammed. This document supplies the
information necessary to reprogram the on-board clock frequencies. GSC has developed routines to calculate and
program the on-board oscillator for a given set of frequencies, so it should not be necessary for the user need the
following information – it is provided for documentation purposes. Please contact GSC for help in setting up the on-
board oscillator.
The CY22393 contains several internal address which contain the programming information. GSC has mirrored this
data internal to the FPGA (CLOCK RAM) to allow the user to simply setup the data in the FPGA RAM and then
command the on-board logic to program the clock chip. This isolates the user from the hardware serial interface to
the chip. For detailed CY22393 programming details, please refer to the Cypress Semiconductor CY22393 dat
sheet.
For the SIO4BX2, a second programmable oscillator has been added to assure that each channel has a dedicated
PLL. (The older SIO4BX uses 3 PLLs in a single CY22393 to generate all four clocks). To implement this, a second
CLOCK RAM block was added. CLOCK RAM1 programs the first CY22393 (using CLKA=Ch1_Clk,
CLKB=Ch2_Clk, CLKC=Ch3_Clk), and CLOCK_RAM2 programs the second CY22393 (using CLKD=Ch4_Clk).
Since the original SIO4BX (with a single CY22393) used CLKD for Ch4_Clk, the same code can be made to
support both schemes by simply programming CLKD of the first CY22393.
Each CLOCK RAM block is accessed through 2 registers – Address Offset at local offset 0x00A0 and Data at local
ffset at 0x00A4 (CLOCK RAM1) or 0x00AC (CLOCK RAM2). The user simply sets the RAM Address register to
the appropriate offset, then reads or writes the the RAM data. The Programmable Osc Control/Status register allows
the user to program the CY22393 or setup the clock post-dividers.
The GSC Local Programmable Clock Registers are defined as follows:
0x00A0 – RAM Address Register
Defines the internal CLOCK RAM address to read/write
0x00A4 – RAM Data1 Register
Provides access to the CLOCK RAM1 pointed to by the RAM Addr Register.
0x00AC – RAM Data2 Register
Provides access to the CLOCK RAM2 pointed to by the RAM Addr Register.
0x00A8 – Programmable Osc Control/Status Register
Provides control to write the contents of the CLOCK RAM to the CY22393 and setup additional post-
dividers for the input clocks.
Control Word (Write Only)
D0
Program Oscillator
1 = Program contents of CLOCK RAM to CY22393.
Automatically resets to 0.
D1
Measure Channel 1 Clock
D2
Measure Channel 2 Clock
D3
Measure Channel 3 Clock
