General Standards Corporation PCIe-SIO4BX2 Скачать руководство пользователя страница 34 | Manualshive

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29

Rev NR

5.2

Termination Resistors

The PCIe-SIO4BX2 transceivers have built in termination resistors for the RS-422/RS485 mode. The built in RS-
422/RS485 termination is a 120 Ohm parallel termination. If desired, the internal termination resistors may be
disabled by setting bit D30 in the Pin Source Register.

The board is designed with socketed external parallel termination (if a different value than the internal termination is
required). The external termination resistors are 8 pin SIPs. There are 8 termination SIPs – RP1-RP4, RP7-RP10.
The external parallel resistors are for RS422/RS485 termination only. Refer to Figure 5-1 for resistor pack locations.

Please contact

[email protected]

if a different termination value is required.

5.3

LEDs

Five bicolor LEDs (D1-D5) are accessible via software.  Refer to Figure 5-1 for these LED locations.

LED D1 is controlled from the Board Control Register.  LED_D1 Red is controlled by D25, and LED_D1 Green is
controlled D24

The remaining 4 LEDs are controlled from D23:D20 of the four Channel Control Registers.  Each Channel Control
Register controls 1 LED.  If D23:D22="10", the Red LED will turn off.  Likewise, if D23:D22="11", the Red LED
will turn on.  D21:D20 controls the Green LED in the pair.

LED_D2 is controlled by Ch 4
LED_D3 is controlled by Ch 3
LED_D4 is controlled by Ch 2
LED_D5 is controlled by Ch 1

.Additionally, if all the LED controls are set to 0 in all four of the Channel Control Registers (power up default), the
LEDs will display the lower 4 bits of the firmware revision in Green LED_D2 to LED_D5.

The remaining LED (D6) display the firmware status. This LED should flash at power up or after a PCIe reset,
then will turn off. The LED should be off during normal operation.

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Содержание PCIe-SIO4BX2

Страница 1: ...2 Software Configurable Transceivers and 32K Byte FIFO Buffers 256K Byte total RS 485 RS 422 V 11 RS 232 V 28 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 878...

Страница 2: ...Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corpor...

Страница 3: ...ge Digital Interface Circuits EIA order number EIA RS 422A EIA 485 Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital Multipoint Systems EIA order number E...

Страница 4: ...BYTE LOCAL OFFSET 0X0050 0X0054 0X0058 0X005C 9 2 1 10 INTERRUPT REGISTERS 9 2 1 11 INTERRUPT CONTROL LOCAL OFFSET 0X0060 10 2 1 12 INTERRUPT STATUS CLEAR LOCAL OFFSET 0X0064 10 2 1 13 INTERRUPT EDGE...

Страница 5: ...CONFIGURATION REGISTERS 26 4 1 2 LOCAL CONFIGURATION REGISTERS 27 4 1 3 RUNTIME REGISTERS 27 4 1 4 DMA REGISTERS 27 4 1 4 1 DMA CHANNEL MODE REGISTER PCI 0X80 0X94 27 CHAPTER 5 HARDWARE CONFIGURATION...

Страница 6: ...nous Serial Data Rates up to 10Mbps Asynchronous Serial Data Rates up to 1Mbps Independent Transmit and Receive FIFOs for each Serial Channel 32K byte each Multi protocol Transceivers support RS422 RS...

Страница 7: ...r and receiver operation Odd Even Space Mark parity Two 16 bit or one 32 bit CRC polynomial Eight Data Encoding methods NRZ NRZB NRZI Mark NRZI Space Biphase Mark Biphase Space Biphase Level and Diffe...

Страница 8: ...nsfers to efficiently move data to and from the board 1 5 General Purpose IO Since some signals may not be used in all applications the SIO4BX2 provides the flexibility to remap unused signals to be u...

Страница 9: ...0x0340 0x03FF Reserved 0x0400 0x043F 0x0400 Channel 4 USC Registers The GSC Firmware Registers are detailed in Section 2 1 The USC Registers are briefly touched on in Section 2 2 of this manual but ar...

Страница 10: ...h 3 Pin Status 000000XX 0x009C D32 Read Only Ch 4 Pin Status 000000XX 0x00A0 D32 Read Write Programmable Osc RAM Addr 00000000 0x00A4 D32 Read Write Programmable Osc RAM Data 1 00000000 0x00A8 D32 Rea...

Страница 11: ...st Mode FIFO Write to Rx FIFO FIFO Read from Tx FIFO D28 27 FIFO Allocation Unused D26 RESERVED D25 LED D1 1 Turn on Red LED D1 D24 LED D1 1 Turn on Green LED D1 D23 Timestamp Clear 0 timestamp counte...

Страница 12: ...4 Timestamp Local Offset 0x000C The timestamp will add a 24 bit timestamp value for each data value in the data stream D31 24 RESERVED D23 0 Current timestamp value 2 1 5 Channel TX Almost Flags Local...

Страница 13: ...D31 8 RESERVED D7 0 Channel FIFO Data 2 1 8 Channel Control Status Local Offset 0x001C 0x002C 0x003C 0x004C The Channel Control Status Register provides the reset functions and data transceiver enable...

Страница 14: ...uest Channel Sync Detect IRQ will be generated The interrupt source must be enabled in the Interrupt Control Register in order for an interrupt to be generated 2 1 10 Interrupt Registers There are 32...

Страница 15: ...ggered the interrupt will occur when the FIFO transitions from NOT EMPTY to EMPTY Likewise if Tx FIFO Empty Interrupt is set as Falling Edge Triggered the interrupt will occur when the FIFO transition...

Страница 16: ...Output source for the Clocks Data RTS and DCD outputs 31 30 29 28 27 26 25 24 Transceiver Enable Termination Disable Loopback Enable DCE DTE Mode Transceiver Protocol Mode 23 22 21 20 19 18 17 16 15...

Страница 17: ...ignals internal to the board D22 Reserved D21 19 Cable TxD Output Control Allows TxD output to be used as a general purpose output D21 D20 D19 TxD Source 0 0 X USC_TxD 0 0 0 Output 0 0 1 1 Output 1 1...

Страница 18: ...t from IO Connector DCD 0X Input 1 0 Reserved XX Don t Care 1 1 Output to IO Connector 1X Output D10 9 USC_CTS Direction Setup If CTS is used as GPIO set this field to 00 and set Pin Source Register D...

Страница 19: ...SC IO Control Reg D2 0 to ensure the signal is not being driven by both the USC and the FPGA D2 D1 D0 USC_TxC Source USC IOCR D5 D3 Setup 0 0 0 Prog Clock 000 Input 0 0 1 Inverted Prog Clock 000 Input...

Страница 20: ...umber of words in Rx FIFO D15 D0 Number of words in Tx FIFO 2 1 15 FIFO Size Register Local Offset 0x00E0 0x00E4 0x00E8 0x00EC The FIFO Size Registers display the sizes of the installed data FIFOs Thi...

Страница 21: ...SC User s Manual These manuals may be obtained directly from Zilog www zilog com or copies of these manuals may be downloaded from the General Standards website www generalstandards com Some specific...

Страница 22: ...nce the user interface to the USC is an 8 bit interface the software only needs to set the lower byte to 0x00 hardware implementation will program the upper byte of the BCR 2 2 3 USC Data Transfer Alt...

Страница 23: ...R Hi Lo Channel Control Register 0x11 0x10 CMCR Hi Lo Clock Mode Control Register 0x13 0x12 HCR Hi Lo Hardware Configuration Register 0x17 0x16 IOCR Hi Lo I O Control Register 0x19 0x18 ICR Hi Lo Inte...

Страница 24: ...Channel Reset The FIFO resets allow each individual FIFO Tx and Rx to be reset independently Setting the FIFO reset bit will clear the FIFO immediately 3 2 FIFOs Deep transmit and receive FIFOs are th...

Страница 25: ...unters report the exact number of data words currently in each FIFO By utilizing this information the user can determine the exact amount of data which can safely be transferred to the transmit FIFOs...

Страница 26: ...channel to have a unique programmable clock ProgClk The IO Connector Clocks consist of a Receive Clock RxC a Transmit Clock TxC and a bidirectional Auxillary Clock AuxC for each channel RxC is always...

Страница 27: ...t method will be to program the channel programmable clock to be 16 32 64 times the desired baudrate and use this clock as the source for the TxC RxC pin Section 2 1 11 describes how to program the Pi...

Страница 28: ...ut configuration for each signal The DCD and AuxC direction is set in the Pin Source register fields independent of DCE DTE mode Signal DTE DCE TxC TxC Out RxC In RxC RxC In TxC Out TxD TxD Out RxD In...

Страница 29: ...I9056 interrupts The single Local Interrupt is made up of the interrupt sources described in Section 2 1 10 In addition the Zilog USC contains a number of interrupt sources which are combined into a s...

Страница 30: ...may be used to determine how much space is available for DMA so that the FIFO will never over under run Demand Mode DMA requires less software control but runs the risk of losing data due to an incom...

Страница 31: ...pts to filter the information from the PCI9056 manual to provide the necessary information for a SIO4BX2 specific driver The SIO4BX2 uses an on board serial EEPROM to initialize many of the PCI9056 re...

Страница 32: ...l Mode Register PCI 0x80 0x94 The DMA Channel Mode register must be setup to match the hardware implementation Bit Description Value Notes D1 0 Local Bus Width 11 32 bit 00 8 bit Although the serial F...

Страница 33: ...d ID in the Board Status Register See Section 2 1 3 This is useful to uniquely identify a board if more than one SIO4BX2 card is in a system When the Board ID jumper is installed it will read 1 in the...

Страница 34: ...or LEDs D1 D5 are accessible via software Refer to Figure 5 1 for these LED locations LED D1 is controlled from the Board Control Register LED_D1 Red is controlled by D25 and LED_D1 Green is controlle...

Страница 35: ...RTS3 CTS3 Unused Hi 12 RTS1 CTS1 RTS1 CTS1 46 RTS3 CTS3 RTS3 CTS3 13 TXD1 RXD1 Unused Hi 47 TXD3 RXD3 Unused Hi 14 TXD1 RXD1 TXD1 RXD1 48 TXD3 RXD3 TXD3 RXD3 15 TXC1 RXC1 Unused Hi 49 TXC3 RXC3 Unuse...

Страница 36: ...the serial channels into eight DB25 connectors Shielded cable options are also available Please consult our sales department for more information on cabling options and pricing 6 2 Device Drivers Gen...

Страница 37: ...mplement this a second CLOCK RAM block was added CLOCK RAM1 programs the first CY22393 using CLKA Ch1_Clk CLKB Ch2_Clk CLKC Ch3_Clk and CLOCK_RAM2 programs the second CY22393 using CLKD Ch4_Clk Since...

Страница 38: ...rogrammable oscillator to provide for slow baud rates Each 4 bit field will allow a post divider of 2 n For example if the post divider value 0 the input clock is not post divided A value of 2 will pr...

Страница 39: ...ved 0x00 0x1A Reserved 0xE9 0x1B Reserved 0x08 0x1C 0x3F Reserved Unused 0x00 0x40 PLL1 Q Setup0 0x00 0x41 PLL1 P Lo 0 Setup0 0x00 0x41 PLL1 Enable PLL1 P Hi Setup0 0x00 0x43 PLL1 Q Setup1 0x00 0x44 P...

Страница 40: ...Offset 0x00 0xE5100100 D31 16 HW Board Rev 0xE510 PCIe SIO4BX2 Rev NR D31 1 Features Register Present D30 1 Complies with this standard D29 1 66MHz PCI bus interface 0 33MHz PCI bus interface D28 1 64...

Страница 41: ...Pin Source Change 0x02 Multi Protocol support 0x03 Common Internal External FIFO Support 0x04 FIFO Latched Underrun Overrun Level 0x05 Demand mode DMA Single Cycle for Tx 0x06 DMA_Single_Cycle_Dis up...

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