General Standards Corporation PCIe-SIO4BX2, Руководство пользователя

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9 Rev NR
D7:0 Channel Control Bits
D7 1 = Reset USC ((Pulsed - will automatically clear to ‘0’)
Notes:

Following a USC Reset, the next access to the USC must be a write of 0x00 to Local
Offset 0x100 (Ch1/2) or Local Offset 0x300 (Ch3/4).

Since two channels share each USC (Ch1 & Ch2, Ch3 & Ch4), resetting a USC will
affect both channel.
D6 1 = Reset Channel (Pulsed - will automatically clear to ‘0’)
D5:D4 RESERVED (FIFO Rx/Tx Allocation )
D3 Receive Status Word Enable
1 = Receive status word (RSR) is saved in data stream with every received data word.
D2 Timestamp Enable
1 = 24-bit timestamp word is saved in data stream with every received data word.
D1 1 = Reset Channel Rx FIFO (Pulsed - will automatically clear to ‘0’)
D0 1 = Reset Channel Tx FIFO (Pulsed - will automatically clear to ‘0’).
2.1.9 Channel Sync Detect Byte: Local Offset 0x0050 / 0x0054 / 0x0058 / 0x005C
The Sync Detect Byte allows an interrupt to be generated when the received data matches the Sync Detect Byte.
D31:8 RESERVED
D7:0 Channel Sync Detect Byte
If the data being loaded into the Receive FIFO matches this data byte, an interrupt request
(Channel Sync Detect IRQ) will be generated. The interrupt source must be enabled in
the Interrupt Control Register in order for an interrupt to be generated.
2.1.10 Interrupt Registers
There are 32 on-board interrupt sources (in addition to USC interrupts and PLX interrupts) which may be
individually enabled. Four interrupt registers control the on-board interrupts – Interrupt Control, Interrupt Status,
Interrupt Edge/Level, and Interrupt Hi/Lo. The 32 Interrupt sources are:
IRQ # Source Default Level Alternate Level
IRQ0 Channel 1 Sync Detected Rising Edge NONE
IRQ1 Channel 1 Tx FIFO Almost Empty Rising Edge Falling Edge
IRQ2 Channel 1 Rx FIFO Almost Full Rising Edge Falling Edge
IRQ3 Channel 1 USC Interrupt Level Hi NONE
IRQ4 Channel 2 Sync Detected Rising Edge NONE
IRQ5 Channel 2 Tx FIFO Almost Empty Rising Edge Falling Edge
IRQ6 Channel 2 Rx FIFO Almost Full Rising Edge Falling Edge
IRQ7 Channel 2 USC Interrupt Level Hi NONE
IRQ8 Channel 3 Sync Detected Rising Edge NONE
IRQ9 Channel 3 Tx FIFO Almost Empty Rising Edge Falling Edge
IRQ10 Channel 3 Rx FIFO Almost Full Rising Edge Falling Edge
IRQ11 Channel 3 USC Interrupt Level Hi NONE
IRQ12 Channel 4 Sync Detected Rising Edge NONE
IRQ13 Channel 4 Tx FIFO Almost Empty Rising Edge Falling Edge