General Standards Corporation PCIe-SIO4BX2, Руководство пользователя

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14 Rev NR
D5:3 USC_RxC Source
The clock source must agree with the USC Clock setup (USC I/O Control Reg D5:3) to ensure
the signal is not being driven by both the USC and the FPGA.
D5 D4 D3 USC_RxC Source USC IOCR D2:D0 Setup
0 0 0 Prog Clock 000 (Input)
0 0 1 Inverted Prog Clock 000 (Input)
0 1 0
‘0’
000 (Input)
0 1 1
‘1’
000 (Input)
1 0 0 Cable RxC Input 000 (Input)
1 0 1 Cable RxAuxC Input 000 (Input)
1 1 0 RESERVED --------
1 1 1 Driven from USC IOCR D2:D0 != 000 (Output)
D2:0
USC_TxC Source
Since this signal is bidirectional (it may be used as either an input or output to the USC), the
clock source must agree with the USC Clock setup (USC IO Control Reg D2:0) to ensure the
signal is not being driven by both the USC and the FPGA.
D2 D1 D0 USC_TxC Source USC IOCR D5:D3 Setup
0 0 0 Prog Clock 000 (Input)
0 0 1 Inverted Prog Clock 000 (Input)
0 1 0
‘0’
000 (Input)
0 1 1
‘1’
000 (Input)
1 0 0 Cable RxC Input 000 (Input)
1 0 1 Cable RxAuxC Input 000 (Input)
1 1 0 RESERVED --------
1 1 1 Driven from USC IOCR D5:D3 != 000 (Output)
2.1.16 Channel Pin Status: Local Offset 0x0090 / 0x0094 / 0x0098 / 0x009C
Unused inputs may be utilized as general purpose input signals. The Channel Pin Status Register allows the input
state of all the IO pins to be monitored. Output signals as well as inputs are included to aid in debug operation.
D31:D10
RESERVED
D9 TxAuxC Output
D8 RxAuxC Input
D7 DCD Output
D6 RTS Output
D5 TxD Output
D4 TxC Output
D3 DCD Input
D2 CTS Input
D1 RxD Input
D0 RxC Input