15
Rev NR
2.1.13
Programmable Clock Registers: Local Offset 0x00A0 / 0x00A4 / 0x00A8 / 0xAC
The Programmable Clock Registers allow the user to program the on-board programmable oscillator and configure
the channel clock post-dividers. As GSC should provide software routines to program the clock, the user should
have no need to access these registers. See section 3.6 for more information.
2.1.14
FIFO Count Register: Local Offset 0x00D0 / 0x00D4 / 0x00D8 / 0x00DC
The FIFO Count Registers display the current number of words in each FIFO. This value, along with the FIFO Size
Registers, may be used to determine the amount of data which can be safely transferred without over-running (or
under-running) the FIFOs.
D31:16
Number of words in Rx FIFO
D15:D0
Number of words in Tx FIFO
2.1.15
FIFO Size Register: Local Offset 0x00E0 / 0x00E4 / 0x00E8 / 0x00EC
The FIFO Size Registers display the sizes of the installed data FIFOs. This value is calculated at power-up This
value, along with the FIFO Count Registers, may be used to determine the amount of data which can be safely
transferred without over-running (or under-running) the FIFOs.
D31:16
Size of installed Rx FIFO
D15:D0
Size of installed Tx FIFO
2.1.16
FW Type ID Register: Local Offset 0x00F8
This register allows boards to change functionality on each channel. Currently, a channel can only be defined as
Standard or Sync. For SIO4BX-Sync information, please refer to the PCIe-SIO4BX2-SYNC manual.
D31:D24
Channel 4 FW Type –> 01 = Standard / 04 = Sync
D23:D16
Channel 3 FW Type –> 01 = Standard / 04 = Sync
D15:D8
Channel 2 FW Type –> 01 = Standard / 04 = Sync
D7:D0
Channel 1 FW Type –> 01 = Standard / 04 = Sync
