2
Rev NR
Functional Diagram:
66MHz
32 bit
PCI
Interface
Control
Logic
32kb
Tx
FIFO
Universal
Serial
Controller
32kb
Rx
FIFO
Prog
Osc
DTE
DCE
Multi-protocol
Transceiver
Chan 1-4
Receiver
Transmitter
PCIe-PCI
Bridge
P1
P
C
Ie
B
u
s
Cable
Interface
68 pin
SCSI
P2
Figure 1-1 Block Diagram of PCIe-SIO4BX2
1.1
Z16C30 Universal Serial Controller
The PCIe-SIO4BX2 is designed around the Z16C30 Universal Serial Controller( USC). The Z16C30 is a dual
channel multi-protocol serial controller which may be software configured to satisfy a wide variety of serial
communications applications. The USC supports most common asynchronous and synchronous serial protocols.
The USC provides many advanced features, including:
Completely independent transmitter and receiver operation
Odd/Even/Space/Mark parity
Two 16-bit or one 32-bit CRC polynomial
Eight Data Encoding methods – NRZ, NRZB, NRZI-Mark, NRZI-Space, Biphase-Mark, Biphase-Space,
Biphase-Level, and Differential Biphase-Level
1.2
Deep Transmit/Receive FIFOs
Data is transferred to/from the serial interface through Transmit and Receive FIFOs. Each of the four serial channels
has an independent Transmit FIFO and a Receive FIFO for a total of eight separate on-board FIFOs. These FIFOs
are always 32k bytes deep. FIFOs allow data transfer to continue to/from the IO interface independent of PCI
interface transfers and software overhead. The required FIFO size may depend on several factors including data
transfer size, required throughput rate, and the software overhead (which will also vary based on OS). Generally,
faster baud rates (greater than 500kbps) will require deeper FIFOs. Deeper FIFOs help ensure no data is lost for
critical systems.
