Freescale Semiconductor SC140 DSP Core, Справочное руководство

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5-22 SC140 DSP Core Reference Manual
Instruction Timing
The read or write for each memory access can be mapped to the execution cycle in which they operate
as follows:
• Cycle 1
— Move read or write without address pre-calculation.
— Bit mask read without address pre-calculation.
— Pop read with shadow SP valid.
• Cycle 2
— Move read or write with address pre-calculation.
— Bit mask read with address pre-calculation.
— Bit mask write without address pre-calculation.
— Pop read with shadow SP invalid.
• Cycle 3
— Bit mask write with address pre-calculation.
Contention may occur when two instructions in an execution set attempt to access the same physical
memory module in the same cycle. The memory system evaluates contention on a cycle-by-cycle basis, not
for the execution set as a whole.
The following conventions apply to the execution of memory access operations:
• Each AGU access operation is performed in its cycle number, independent of any other access.
• Operations that execute in different cycles are performed in cycle sequence without contention.
• Bit mask instructions (such as BMSET, BMCLR, and BMCHG) are read-modify-write
instructions. These instructions each generate two memory accesses in sequence.
• Pop instruction timing depends on the validity of the stack pointer (SP) shadow register that holds
a pre-decremented value of the SP in order to avoid the need for pre-calculation. If shadow SP is
not valid (for example, after an explicit SP update), another cycle is needed for the first pop in
order to perform the pre-calculation.
The following rules apply to cases of contention due to dual access to the same physical memory module
by two instructions in the same cycle:
• A memory read instruction executes before a memory write instruction.
• For two memory writes to different locations, the order is undefined, meaning that it is
implementation-specific. The program algorithm should not assume any specific behavior of the
memory system for the memory writes.
• Two memory writes to the same location in the same execution set is not allowed by the SC140
programming rules. If this occurs, the memory results are undefined.
5.3.3.1 Memory Access Examples
This section describes the contention cases of two memory access instructions grouped in a VLES. If two
memory writes are grouped in a VLES, it is assumed that the two write addresses contend for the same
physical memory module but do not access the same memory locations. Two memory writes to the same
location are not allowed per
Section 7.6, “Dynamic Programming Rules.” The following description is
assumes a simple memory without write buffers, where the memory system executes all accesses on a