Freescale Semiconductor MC9S08PT60, Справочное руководство

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The MTIM counter (MTIM_CNT) has three modes of operation: stopped, free-running,
and modulo. Out of reset, the counter is stopped. If the counter is started without writing
a new value to the modulo register, then the counter will be in free-running mode. The
counter is in modulo mode when a value other than 0x00 is in the modulo register while
the counter is running.
After any MCU reset, the counter is stopped and reset to 0x00, and the modulus is set to
0x00. The bus clock is selected as the default clock source and the prescale value is
divide by 1. To start the MTIM in free-running mode, simply write to the MTIM status
and control register (MTIM_SC), and clear the MTIM stop bit (TSTP).
Four clock sources are software selectable: the internal bus clock, the fixed frequency
clock (XCLK), and an external clock on the TCLK pin, selectable as incrementing on
either rising or falling edges. The MTIM clock select bits, CLKS1:CLKS0, in
MTIM_CLK are used to select the desired clock source. If the counter is active
(SC[TSTP] = 0) when a new clock source is selected, the counter will continue counting
from the previous value using the new clock source.
Nine prescale values are software selectable: clock source divided by 1, 2, 4, 8, 16, 32,
64, 128, or 256. The prescaler select bits (CLK[PS]) in MTIM_CLK select the desired
prescale value. If the counter is active (SC[TSTP] = 0) when a new prescaler value is
selected, the counter will continue counting from the previous value using the new
prescaler value.
The MTIM modulo register (MTIM_MOD) allows the overflow compare value to be set
to any value from 0x01 to 0xFF. Reset clears the modulo value to 0x00, which results in
a free running counter.
When the counter is active (SC[TSTP] = 0), the counter increments at the selected rate
until the count matches the modulo value. When these values match, the counter
overflows to 0x00 and continues counting. The MTIM overflow flag (SC[TOF]) is set
whenever the counter overflows. The flag sets on the transition from the modulo value to
0x00. Writing to MTIM_MOD while the counter is active resets the counter to 0x00 and
clears SC[TOF].
Clearing SC[TOF] is a two-step process. The first step is to read the MTIM_SC register
while SC[TOF] is set. The second step is to write a 0 to SC[TOF]. If another overflow
occurs between the first and second step, the clearing process is reset and SC[TOF] will
remain set after the second step is performed. This will prevent the second occurrence
from being missed. SC[TOF] is also cleared when a 1 is written to SC[TRST] or when
any value is written to the MTIM_MOD register.
Chapter 13 8-bit modulo timer (MTIM)
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc. 403