Freescale Semiconductor MC9S08PT60, Справочное руководство

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SCG_C3 field descriptions (continued)
Field Description
0 Bus clock to the SCI2 module is disabled.
1 Bus clock to the SCI2 module is enabled.
5
SCI1
SCI1 Clock Gate Control
This bit controls the clock gate to the SCI1 module.
0 Bus clock to the SCI1 module is disabled.
1 Bus clock to the SCI1 module is enabled.
4
SCI0
SCI0 Clock Gate Control
This bit controls the clock gate to the SCI0 module.
0 Bus clock to the SCI0 module is disabled.
1 Bus clock to the SCI0 module is enabled.
3
SPI1
SPI1 Clock Gate Control
This bit controls the clock gate to the SPI1 module.
0 Bus clock to the SPI1 module is disabled.
1 Bus clock to the SPI1 module is enabled.
2
SPI0
SPI0 Clock Gate Control
This bit controls the clock gate to the SPI0 module.
0 Bus clock to the SPI0 module is disabled.
1 Bus clock to the SPI0 module is enabled.
1
IIC
IIC Clock Gate Control
This bit controls the clock gate to the IIC module.
0 Bus clock to the IIC module is disabled.
1 Bus clock to the IIC module is enabled.
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8.7.4 System Clock Gating Control 4 Register (SCG_C4)
This high page register contains control bits to enable or disable the bus clock to the
ACMP, ADC, IRQ, TSI, and KBI modules. Gating off the clocks to unused peripherals is
used to reduce the MCU's run and wait currents.
NOTE
User software should disable the peripheral before disabling the
clocks to the peripheral. When clocks are re-enabled to a
peripheral, the peripheral registers need to be re-initialized by
user software.
System clock gating control registers
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
226 Freescale Semiconductor, Inc.