Freescale Semiconductor DSP56002, Руководство пользователя

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SIGNAL DESCRIPTIONS
2 - 8 DSP56002 PIN DESCRIPTIONS MOTOROLA
register, setting the chip’s operating mode. The chip also samples the PINIT pin and
writes its information into the PEN bit of the PLL Control Register, and it samples the CKP
pin to determine the polarity of the CKOUT signal. When the chip comes out of the reset
state, deassertion occurs at a voltage level and is not directly related to the rise time of
the RESET signal. However, the probability that noise on RESET will generate multiple
resets increases with increasing rise time of the RESET signal.
2.2.4 Power and Clock
The power and clock signals are presented in the following paragraphs.
2.2.4.1 Power (Vcc), Ground (GND)
There are six sets of power and ground pins: a set of eight (four power, four ground) for
internal logic; a set of eight (three power, five ground) for the address bus output buffer;
a set of nine (three power, six ground) for the data bus output buffer; a set of eleven (four
power, seven ground) for ports B and C and for the OnCE; a set of one power and one
ground for the PLL; and a set of one power and one ground for the CKOUT pin. Refer to
the pin assignments in the Layout Practices section of the
DSP56002 Technical Data
Sheet (DSP56002/D).
2.2.4.2 External Clock/Crystal Input (EXTAL)
The EXTAL input interfaces the internal crystal oscillator input to an external crystal or an
external clock.
2.2.4.3 Crystal Output (XTAL)
This output connects the internal crystal oscillator output to an external crystal. If an ex-
ternal clock is used, XTAL should not be connected. It may be disabled through software
control using the XTLD bit in the PLL control register.
2.2.5 Host Interface
The following paragraphs discuss the host interface signals, which provide a convenient
connection to another processor through Port B on the DSP56002.
2.2.5.1 Host Data Bus (H0–H7)
This bidirectional data bus transfers data between the host processor and the DSP56002.
It acts as an input unless HEN is asserted and HR/W is high, making H0–H7 become out-
puts and allowing the host processor to read DSP56002 data. It is high impedance when
HEN is deasserted. H0–H7 can be programmed as general-purpose I/O pins (PB0–PB7)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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