Freescale Semiconductor DSP56002, Руководство пользователя

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INTRODUCTION
MOTOROLA PORT A 4 - 3
4.1 INTRODUCTION
Port A provides a versatile interface to external memory, allowing economical connection
with fast memories/devices, slow memories/devices, and multiple bus master systems.
Port A has two power-reduction features. It can access internal memory spaces, toggling
only the external memory signals that need to change, thereby eliminating unneeded
switching current. Also, if conditions allow the processor to operate at a lower memory
speed, wait states can be added to the external memory access to significantly reduce
power while the processor accesses those memories.
4.2 PORT A INTERFACE
The DSP56002 processor can access one or more of its memory sources (X data mem-
ory, Y data memory, and program memory) while it executes an instruction. The memory
sources may be either internal or external to the DSP. Three address buses (XAB, YAB,
and PAB) and four data buses (XDB, YDB, PDB, and GDB) are available for internal
memory accesses during one instruction cycle. Port A’s one address bus and one data
bus are available for external memory accesses.
If all memory sources are internal to the DSP, one or more of the three memory sources
may be accessed in one instruction cycle (i.e., program memory access or program mem-
ory access plus an X, Y, XY, or L memory reference). However, when one or more of the
memories are external to the chip, memory references may require additional instruction
cycles because only one external memory access can occur per instruction cycle.
If an instruction cycle requires more than one external access, the processor will make
the accesses in the following priority: X memory, Y memory, and program memory. It
takes one instruction cycle for each external memory access – i.e., one access can be
executed in one instruction cycle, two accesses take two instruction cycles, etc. Since the
external data bus is only 24 bits wide, one XY or long external access will take two instruc-
tion cycles. The 16-bit address bus can sustain a rate of one memory access per
instruction cycle (using no-wait-state memory which is discussed in
4.4 PORT A WAIT
STATES ).
Figure 4-1 shows the port A signals divided into their three functional groups: address bus
signals (A0-A15), data bus signals (D0-D15), and bus control. The bus control signals can
be subdivided into three additional groups: read/write control (RD and WR), address
space selection (including program memory select (PS), data memory select (DS), and
X/Y select) and bus access control (BN, BR, BG, WT, BS).
The read/write controls can act as decoded read and write controls, or, as seen in Figure
4-2, Figure 4-3, and Figure 4-4, the write signal can be used as the read/write control, and
the read signal can be used as an output enable (or data enable) control for the memory.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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