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SIGNAL DESCRIPTIONS

MOTOROLA

DSP56002 PIN DESCRIPTIONS

2 - 5

2.2.2.2

Data Memory Select (DS)

This three-state output is asserted only when external data memory is referenced (see Table 2-1).

2.2.2.3

X/Y Select (X/Y)

This three-state output selects which external data memory space (X or Y) is referenced
by DS (see Table 2-1).

2.2.2.4

Read Enable (RD)

This three-state output is asserted to read external memory on the data bus (D0–D23).

2.2.2.5

Write Enable (WR)

This three-state output is asserted to write external memory on the data bus (D0–D23).

2.2.2.6

Bus Needed (BN)

The BN output pin is asserted whenever the chip requires the external memory expansion
port (Port A). During instruction cycles where the external bus is not required, BN is deas-
serted.

If an external device has requested the bus by asserting the BR input and the DSP

has granted the bus (by asserting BG), the DSP will continue processing as long as no
external accesses are required. If an external access is required and the chip is not the
bus master, it will stop processing and remain in wait states until bus ownership is re-
turned. If the BN pin is asserted when the chip is not the bus master, this indicates that
processing has stopped and the DSP is waiting to acquire bus ownership. An external ar-
biter may use this pin to help decide when to return bus ownership to the DSP.

Note:

The BN pin cannot be used as an early indication of imminent external bus access
because it is valid later than the other bus control signal BS.

During hardware reset, BN is deasserted.

2.2.2.7

Bus Request (BR)

When the bus request input (BR) is asserted, the DSP56002 will always relinquish the bus
to an external device such as a processor or DMA controller. The external device will be-
come the new master of the external address and data buses while the DSP continues
internal operations using internal memory spaces. When BR is deasserted, the
DSP56002 will again assume bus mastership.

When BR is asserted, the DSP56002 will always release Port A, including A0–A15, D0–
D23, and the bus control pins (PS, DS, X/Y, RD, WR, and BS) by placing them in the high-
impedance state, after the execution of the current instruction has been completed.

Note:

To prevent erroneous operation, the BR pin should be pulled up when it is not in use.

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Содержание DSP56002

Страница 1: ...SER S MANUAL Motorola Inc Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin Texas 78735 8598 Freescale Semiconductor I Freescale Semiconductor Inc For More Information O...

Страница 2: ...2 2 1 Program Memory Select PS 2 4 2 2 2 2 Data Memory Select DS 2 5 2 2 2 3 X Y Select X Y 2 5 2 2 2 4 Read Enable RD 2 5 2 2 2 5 Write Enable WR 2 5 2 2 2 6 Bus Needed BN 2 5 2 2 2 7 Bus Request BR...

Страница 3: ...7 Synchronous Serial Interface SSI 2 10 2 2 7 1 Serial Clock Zero SC0 2 10 2 2 7 2 Serial Control One SC1 2 11 2 2 7 3 Serial Control Two SC2 2 11 2 2 7 4 SSI Serial Clock SCK 2 11 2 2 7 5 SSI Receiv...

Страница 4: ...3 11 3 4 6 Bootstrap From Host Mode 5 3 11 3 4 7 Bootstrap From SCI Mode 6 3 12 3 4 8 Reserved Mode 7 3 12 3 5 DSP56002 INTERRUPT PRIORITY REGISTER 3 12 3 6 DSP56002 PHASE LOCKED LOOP PLL MULTIPLICAT...

Страница 5: ...R Host Command Pending HCP Bit 2 5 16 5 3 2 2 4 HSR Host Flag 0 HF0 Bit 3 5 16 5 3 2 2 5 HSR Host Flag 1 HF1 Bit 4 5 16 5 3 2 2 6 HSR Reserved Status Bits 5 and 6 5 17 5 3 2 2 7 HSR DMA Status DMA Bit...

Страница 6: ...s HA0 HA2 5 31 5 3 4 3 Host Read Write HR W 5 32 5 3 4 4 Host Enable HEN 5 32 5 3 4 5 Host Request HREQ 5 32 5 3 4 6 Host Acknowledge HACK 5 32 5 3 5 Servicing the Host Interface 5 33 5 3 5 1 HI Host...

Страница 7: ...2 1 9 SCR Idle Line Interrupt Enable ILIE Bit 10 6 20 6 3 2 1 10 SCR SCI Receive Interrupt Enable RIE Bit 11 6 21 6 3 2 1 11 SCR SCI Transmit Interrupt Enable TIE Bit 12 6 21 6 3 2 1 12 SCR Timer Int...

Страница 8: ...ting Mode 6 6 71 6 3 11 Example Circuits 6 74 6 4 SYNCHRONOUS SERIAL INTERFACE SSI 6 76 6 4 1 SSI Data and Control Pins 6 78 6 4 1 1 Serial Transmit Data Pin STD 6 78 6 4 1 2 Serial Receive Data Pin S...

Страница 9: ...6 4 2 3 7 SSISR SSI Transmit Data Register Empty TDE Bit 6 6 97 6 4 2 3 8 SSISR SSI Receive Data Register Full RDF Bit 7 6 97 6 4 2 3 9 SSI Receive Shift Register 6 97 6 4 2 3 10 SSI Receive Data Reg...

Страница 10: ...4 9 Data Output DO Bit 10 7 7 7 4 10 TCSR Reserved bits Bits 11 23 7 7 7 5 TIMER EVENT COUNTER MODES OF OPERATION 7 7 7 5 1 Timer Mode 0 Standard Timer Mode Internal Clock No Timer Output 7 7 7 5 2 T...

Страница 11: ...iod Measurement Mode Timer Mode 5 7 22 APPENDIX A BOOTSTRAP AND ROM CODE A 1 INTRODUCTION A 3 APPENDIX B PROGRAMMING SHEETS B 1 PERIPHERAL ADDRESSES B 3 B 2 INTERRUPT VECTOR ADDRESSES B 4 B 3 INSTRUCT...

Страница 12: ...4 8 Mixed Speed Expanded System 4 12 4 9 Bus Control Register 4 14 4 10 Bus Strobe Wait Sequence 4 15 4 11 Bus Request Bus Grant Sequence 4 17 4 12 Bus Arbitration Using Only BR and BG with Internal C...

Страница 13: ...5 42 5 22 Host Mode and INIT Bits 5 43 5 23 Bits Used for Host to DSP Transfer 5 44 5 24 Data Transfer from Host to DSP 5 45 5 25 Receive Data from Host Main Program 5 46 5 26 Receive Data from Host...

Страница 14: ...19 Synchronous Timing 6 43 6 20 SCI Synchronous Transmit 6 44 6 21 SCI Synchronous Receive 6 45 6 22 Asynchronous SCI Receiver Initialization 6 46 6 23 SCI Character Reception 6 47 6 24 SCI Character...

Страница 15: ...ous Clock Timing Diagram 8 Bit Example 6 117 6 60 Internally Generated Clock Timing 8 Bit Example 6 118 6 61 Externally Generated Gated Clock Timing 8 Bit Example 6 119 6 62 Synchronous Communication...

Страница 16: ...ter Module Block Diagram 7 3 7 2 Timer Event Counter Programming Model 7 4 7 3 Standard Timer Mode Mode 0 7 8 7 4 Timer Event Counter Disable 7 9 7 5 Standard Timer Mode Internal Clock Output Pulse En...

Страница 17: ...8 Command Vector Register CVR B 18 B 19 Interrupt Control Register ICR B 18 B 20 Interrupt Status Register ISR B 19 B 21 Interrupt Vector Register IVR B 19 B 22 Receive Byte Registers B 20 B 23 Transm...

Страница 18: ...TOROLA LIST of FIGURES xix List of Figures Continued Figure Page Number Title Number Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com...

Страница 19: ...ous SCI Bit Rates for a 40 MHz Crystal 6 36 6 3b Frequencies for Exact Asynchronous SCI Bit Rates 6 36 6 4a Synchronous SCI Bit Rates for a 32 768 MHz Crystal 6 37 6 4b Frequencies for Exact Synchrono...

Страница 20: ...le Page Number Title Number APPENDIX B B 1 B 1 Interrupts Starting Addresses and Sources B 4 B 2 Instruction Set Summary Sheet 1 of 5 B 5 Freescale Semiconductor I Freescale Semiconductor Inc For More...

Страница 21: ...Please send your suggestions corrections to the Fax number or Email address above or mail this completed form to Motorola Inc 6501 Wm Cannon Drive West Austin Texas 78735 8598 Attn DSP Applications D...

Страница 22: ...sections that you feel need improvement 3 What sections of this manual do you consider most important least important DSP56002 User s Manual Trouble Report Freescale Semiconductor I Freescale Semicon...

Страница 23: ...to after the JCS instruction Replace RTI with RTI X Replace FLAG MOVE A R3 with FLAG MOVE A X R3 Page 6 68 Section 6 3 9 third sentence Replace Bits CD11 CD0 SCP and STIR in the SCCR work together to...

Страница 24: ...r I O 3 Serial Comm SCI or I O 15 Host Interface HI or I O 16 bit Bus 24 bit Bus External Address Bus Switch Data 24 External Data Bus Switch Control 10 Bus Control Data ALU 24 24 56 56 bit MAC Two 56...

Страница 25: ...MOTOROLA DSP56002 User s Manual Addendum 3 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 26: ...1 Yes 2 Reset 000000 Register IPR 23 22 21 20 19 18 16 17 0 0 0 0 0 0 0 0 0 0 SSL1 SSL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SCL1 SCL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SCL1...

Страница 27: ...MOTOROLA DSP56002 User s Manual Addendum 5 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 28: ...rrupt Enable 0 Disable 1 Enable Receive Enable 0 Disable 1 Enable Transmit Interrupt Enable 0 Disable 1 Enable Gated Clock Control 0 Continuous Clock 1 Gated Clock Output Flag x If SYN 1 and SCD1 1 OF...

Страница 29: ...imer Control Bits 3 5 TC0 TC2 TC2 TC1 TC0 TIO Clock Mode 0 0 0 GPIO Internal Timer 0 0 1 Output Internal Timer Pulse 0 1 0 Output Internal Timer Toggle 0 1 1 X X Undefined 1 0 0 Input Internal Input W...

Страница 30: ...its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications...

Страница 31: ...ins The MAIN PROGRAM in Figure 5 25 initializes Page 7 4 Change In Timer Modes 4 and 5 to read In Timer Modes 4 5 and 6 in the first line of the last paragraph Page 7 6 In the second paragraph of sect...

Страница 32: ...nal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subs...

Страница 33: ...MOTOROLA 1 1 SECTION 1 INTRODUCTION TO THE DSP56002 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 34: ...6002 MOTOROLA 1 1 INTRODUCTION 1 3 1 2 FEATURES 1 4 1 3 DSP56K CENTRAL PROCESSING UNIT OVERVIEW 1 4 1 4 MANUAL ORGANIZATION 1 5 Freescale Semiconductor I Freescale Semiconductor Inc For More Informati...

Страница 35: ...The DSP56002 Technical Data Sheet DSP56002 D provides timing pinout and packaging descriptions see Figure 1 1 This section presents the DSP56002 features Central Processor and central processor instru...

Страница 36: ...it Timer Event Counter On chip Emulator OnCE for Unobtrusive Full Speed Debugging Optional Program Security Feature Disables Unauthorized Program ROM and OnCE Access PLL Based Clocking with Wide Input...

Страница 37: ...ains the various operating modes that affect the processor s program and data memories SECTION 4 PORT A describes the external memory port its registers and control signals SECTION 5 PORT B describes...

Страница 38: ...CH BUS CONTROL EXTERNAL DATA BUS SWITCH ADDRESS DATA 16 BITS 24 BITS PORT A PLL ADDRESS GENERATION UNIT OnCE EXPANSION AREA CONTROL 24 Bit 56K CPU Figure 1 2 DSP56002 Block Diagram Program Control Uni...

Страница 39: ...MOTOROLA 2 1 SECTION 2 DSP56002 PIN DESCRIPTIONS Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 40: ...IPTIONS MOTOROLA 2 1 INTRODUCTION 2 3 2 2 SIGNAL DESCRIPTIONS 2 3 2 3 ON CHIP EMULATION OnCE PINS 2 11 2 4 PLL PINS 2 14 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On T...

Страница 41: ...All unused inputs should have pull up resistors for two reasons 1 floating inputs draw excessive power and 2 a floating input can cause erroneous operation For Functional Group Number of Pins Port A...

Страница 42: ...igh impedance state when the bus grant signal is asserted 2 2 2 Port A Bus Control The Port A bus control signals are discussed in the following paragraphs The bus control signals provide a means to c...

Страница 43: ...If the BN pin is asserted when the chip is not the bus master this indicates that processing has stopped and the DSP is waiting to acquire bus ownership An external ar biter may use this pin to help d...

Страница 44: ...2 D for timing details 2 2 3 Interrupt and Mode Control The interrupt and mode control pins select the chip s operating mode as it comes out of hardware reset and they receive interrupt requests from...

Страница 45: ...tiple interrupts also increases 2 2 3 3 Mode Select C Non Maskable Interrupt Request MODC NMI This input pin works with the MODA and MODB pins to select the chip s operating mode and it receives an i...

Страница 46: ...he PLL and a set of one power and one ground for the CKOUT pin Refer to the pin assignments in the Layout Practices section of the DSP56002 Technical Data Sheet DSP56002 D 2 2 4 2 External Clock Cryst...

Страница 47: ...w H0 H7 become inputs When HEN is deasserted host data is latched inside the DSP Normally a chip select signal derived from host address decoding and an enable clock are used to generate HEN HEN can b...

Страница 48: ...ured as a GPIO input pin during hardware reset 2 2 6 3 SCI Serial Clock SCLK This bidirectional pin provides an input or output clock from which the transmit and or re ceive baud rate is derived in th...

Страница 49: ...bit rate clock for the SSI when only one clock is being used SCK can be programmed as a general purpose I O pin PC6 when it is not needed as an SSI pin and it is configured as a GPIO input pin during...

Страница 50: ...s see SECTION 10 ON CHIP EMULATION OnCE in the DSP56000 Family Manual It is an output when the chip is not in debug mode During hardware reset this pin is defined as an output and is driven low Note T...

Страница 51: ...should be well regulated and the pin should be pro vided with an extremely low impedance path to the Vcc power rail PVcc should be bypassed to PGND by a 0 1 F capacitor located as close as possible to...

Страница 52: ...r The PEN bit enables the PLL by causing it to derive the internal clocks from the PLL VCO output When the bit is clear the PLL is disabled and the chip s inter nal clocks are derived from the clock c...

Страница 53: ...MOTOROLA 3 1 SECTION 3 MEMORY MODULES AND OPERATING MODES Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 54: ...AND PROGRAM MEMORY 3 3 3 3 DSP56002 OPERATING MODE REGISTER OMR 3 4 3 4 DSP56002 OPERATING MODES 3 7 3 5 DSP56002 INTERRUPT PRIORITY REGISTER 3 12 3 6 DSP56002 PHASE LOCKED LOOP PLL MULTIPLICATION FAC...

Страница 55: ...t vectors and priorities and describes the effect of a hardware reset on the PLL multiplication factor 3 2 DSP56002 DATA AND PROGRAM MEMORY The DSP56002 has 512 words of program RAM 64 words of bootst...

Страница 56: ...om the YAB and 24 bit data trans fers to the data ALU occur on the YDB Y memory may be expanded to 64K off chip Note The off chip peripheral registers should be mapped into the top 64 locations FFC0 F...

Страница 57: ...ACE FFFF 0 DE and YD BITS IN THE OMR DETERMINE THE X AND Y DATA MEMORY MAPS 01FF 00FF Figure 3 1 DSP56002 Memory Maps EXTERNAL PERIPHERALS EXTERNAL PERIPHERALS EXTERNAL Y DATA MEMORY PERIPHERALS INTER...

Страница 58: ...lears the DE bit 3 3 3 Internal Y Memory Disable Bit Bit 3 Bit 3 is defined as Internal Y Memory Disable YD When set all Y Data Memory address es are considered to be external disabling access to inte...

Страница 59: ...g enough to allow a clock stabilization period for the internal clock to begin oscillating and to stabilize See the DSP56002 Technical Data Sheet DSP56002 D for the actual timing values When a stable...

Страница 60: ...tion 0000 in mode 0 and vectors to location E000 in mode 2 3 4 2 Bootstrap From EPROM Mode 1 The bootstrap modes allow the DSP to load a program from an inexpensive byte wide ROM into internal program...

Страница 61: ...d as shown in Table 3 3 Organization of EPROM Data Contents ADDRESS OF EXTERNAL BYTE WIDE P MEMORY P C000 P C001 P C002 P C5FD P C5FE P C5FF CONTENTS LOADED TO INTERNAL P RAM AT P 0000 LOW BYTE P 0000...

Страница 62: ...ion 0000 in the bootstrap ROM The boot strap ROM program loads program RAM from the external byte wide EPROM starting at P C000 4 The bootstrap ROM program ends the bootstrap operation and begins exec...

Страница 63: ...the boot strap program overlays the interrupt vectors 3 4 3 Normal Expanded Mode Mode 2 In this mode the internal program RAM is enabled and the hardware reset vectors to lo cation E000 The memory ma...

Страница 64: ...s program execution starts at the ad dress where the first instruction was loaded The SCI is programmed to work in asynchronous mode with 8 data bits 1 stop bit and no parity The clock source is exter...

Страница 65: ...gister The DSP56002 PLL multiplication factor is set to 1 during hardware reset which means that the Multiplication Factor Bits MF0 MF11 in the PLL Control Register PCTL are set to 000 SSI IPL SCI IPL...

Страница 66: ...tatus P 0014 0 2 SCI Receive Data P 0016 0 2 SCI Receive Data with Exception Status P 0018 0 2 SCI Transmit Data P 001A 0 2 SCI Idle Line P 001C 0 2 SCI Timer P 001E 3 NMI P 0020 0 2 Host Receive Data...

Страница 67: ...st Receive Data Interrupt Host Transmit Data Interrupt SSI RX Data with Exception Interrupt SSI RX Data Interrupt SSI TX Data with Exception Interrupt SSI TX Data Interrupt SCI RX Data with Exception...

Страница 68: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 69: ...MOTOROLA 4 1 SECTION 4 PORT A Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 70: ...3 4 3 PORT A TIMING 4 9 4 4 PORT A WAIT STATES 4 13 4 5 BUS CONTROL REGISTER BCR 4 13 4 6 BUS STROBE AND WAIT PINS 4 15 4 7 BUS ARBITRATION AND SHARED MEMORY 4 16 Freescale Semiconductor I Freescale S...

Страница 71: ...memories are external to the chip memory references may require additional instruction cycles because only one external memory access can occur per instruction cycle If an instruction cycle requires m...

Страница 72: ...CH EXTERNAL DATA BUS D0 D23 X DATA XD Y DATA YD PROGRAM DATA PD 24 BIT INTERNAL DATA BUSES 24 GLOBAL DATA GD EXTERNAL BUS CONTROL LOGIC BUS CONTROL SIGNALS RD READ ENABLE WR WRITE ENABLE PS PROGRAM ME...

Страница 73: ...l inputs require either faster RAM chips or external data buffers to avoid data bus buffer conflicts Figure 4 2 shows an example of external program memory A typical implementation of this circuit wou...

Страница 74: ...the development mode an exception fetch to any interrupt vector location will cause the X Y signal to go low when PS is asserted This procedure is useful for debugging and for allowing external circui...

Страница 75: ...EMORY 3000 2FFF 2K X DATA MEMORY 27FF 2K Y DATA MEMORY 2000 24 BITS U2 Figure 4 4 Memory Segmentation PS DS X Y External Memory Reference 1 1 1 No Activity 1 0 1 X Data Memory on Data Bus 1 0 0 Y Data...

Страница 76: ...ROM RESET FUNCTION FROM OPEN COLLECTOR BUFFER A0 A10 D0 D7 A0 A9 A10 CS WE OE RD PS X Y DS WR CE A0 A10 2716 D0 D23 11 10 2018 55 3 D0 D23 BR HACK MBD301 MODC NMI WT DR Notes 1 These diodes must be Sc...

Страница 77: ...clock see Figure 4 6 and Fig ure 4 7 are provided in the DSP56002 Advance Information Data Sheet DSP56002 D This timing is essential for designing synchronous multiprocessor systems Figure 4 6 shows...

Страница 78: ...ps These chip select sig nals change the memory chips from low power standby mode to active mode and begin the read access time This mode change allows slower memories to be used since the chip select...

Страница 79: ...ecomes an input 3 Wait states are inserted into the bus cycle by a wait state counter or by assert ing WT The wait state counter is loaded from the bus control register If the value loaded into the wa...

Страница 80: ...D CS RD D A0 A15 D0 D23 CS CS WE OE CS OE CE OE 6242 15 6242 15 2764 25 2764 25 2764 25 27256 30 27256 30 27256 30 8K x 24 X RAM 150 ns 4 WAIT STATES 8K x 24 Y ROM 250 ns 8 WAIT STATES 32K x 24 P ROM...

Страница 81: ...t states are executed until the external device releases the DSP to finish the external memory cycle 4 5 BUS CONTROL REGISTER BCR The BCR determines the expansion bus timing by controlling the timing...

Страница 82: ...P memory uses five wait states and the analog converters use 14 wait states Controlling five different devices at five dif ferent speeds requires only one additional logic package Half the gates in th...

Страница 83: ...bus access and provides another means of halting the DSP at a known program location with a fast restart The timing of the BS and WT pins is illustrated in Figure 4 10 Every external access BS is ass...

Страница 84: ...ct additional bus masters which may be additional DSPs microprocessors direct memory access DMA controllers etc to the port A bus They work together to arbitrate and determine what device gets access...

Страница 85: ...wever the data lines will remain in three state All signals are now ready for a normal external access During the wait state see Section 7 in the DSP56000 Family Manual the BR and BG circuits remain a...

Страница 86: ...l the bus 4 DSP 2 accesses the bus for block transfers etc at full speed 5 To release the bus DSP 2 sets OUT2 0 BR 2 0 after the last external access 6 DSP 2 then sets OUT1 1 BR 1 1 to return control...

Страница 87: ...BANK DSP56002 1 DSP56002 2 BUS ARBITER Figure 4 12 Bus Arbitration Using Only BR and BG with Internal Control DATA TRANSFERRED OUT1 1 2 3 4 5 6 7 IN1 OUT2 Figure 4 13 Two DSPs with External Bus Arbitr...

Страница 88: ...that BR 2 is deasserted Hence BG of DSP 2 is deasserted which three states the buffers giving DSP 2 control of the memory 16 SYSTEM MEMORY 32K x 24 X DATA RAM 32K x 24 Y DATA RAM 32K x 24 PROGRAM RAM...

Страница 89: ...enables the three state buffers placing the DSP 1 signals on the memory bus Asserting BG also deasserts WT which allows DSP 1 to finish its bus cycle 3 When DSP 1 s memory cycle is complete it release...

Страница 90: ...memory system when separate test and set instructions are used to lock a data block for use by a single processor The correct procedure is to test the semaphore and then set the semaphore if it was cl...

Страница 91: ...in the DSP56000 Family Manual The proper way to set the semaphore to gain exclusive access to a memory block is to use BSET to test the semaphore and to set it to one After the bit is set the result o...

Страница 92: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 93: ...MOTOROLA 5 1 SECTION 5 PORT B Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 94: ...ORT B MOTOROLA 5 1 INTRODUCTION 5 3 5 2 GENERAL PURPOSE I O CONFIGURATION 5 4 5 3 HOST INTERFACE HI 5 10 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go t...

Страница 95: ...amples of how to configure and use the port EXTERNAL ADDRESS SWITCH EXTERNAL DATA SWITCH BUS CONTROL HOST DMA PARALLEL INTERFACE SCI INTERFACE SSI INTERFACE PORT A I 0 47 PORT C I 0 9 PORT B I 0 15 A0...

Страница 96: ...is set to one If a pin is configured as a GPIO input as shown in Figure 5 4 and the processor reads the PBD the processor sees the logic level on the pin If the processor writes to the PBD the data i...

Страница 97: ...Note The external host processor should be carefully synchronized to the DSP56002 to assure that the DSP and the external host will properly read status bits transmitted between them There is more di...

Страница 98: ...either X or Y memory The bit oriented instructions that use I O short addressing BCHG BCLR BSET BTST JCLR JSCLR JSET and JSSET can also be used to address individual bits for faster I O processing The...

Страница 99: ...REGISTER SCCR SCI INTERFACE STATUS REGISTER SSR SCI INTERFACE CONTROL REGISTER SCR SSI RECIEVE TRANSMIT DATA REGISTER RX TX SSI STATUS TIME SLOT REGISTER SSISR TSR SSI CONTROL REGISTER B CRB SSI CONT...

Страница 100: ...instruction cycle For example the instruction MOVE DATA15 X PORTB DATA24 Y EXTERN 1 writes 15 bits of data to the Port B register but the output pins do not change until the following instruction cyc...

Страница 101: ...r allowing the address space to be extended from 64K words 16 bits to two billion words 16 bits 15 bits 31 bits BC 0 BD 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 BD 8 BD 9 BD 10 BD 11 BD 12 BD 13 BD 14 PB...

Страница 102: ...is pre sented in the following listing Speed 3 3 Million Word Sec Interrupt Driven Data Transfer Rate This is the maximum interrupt rate for the DSP56002 running at 40 MHz i e one interrupt every six...

Страница 103: ...y can also be divided horizontally into control at the top DSP to host data transfer in the middle HTX RXH RXM and RXL and host to DSP data transfer at the bottom THX TXM TXL and HRX 5 3 1 Host Interf...

Страница 104: ...processor programming model is shown in Figure 5 12 RECEIVE BYTE REGISTERS READ ONLY TRANSMIT BYTE REGISTERS WRITE ONLY INTERRUPT CONTROL REGISTER READ WRITE DSP CPU GLOBAL DATA BUS 0 ICR 1 CVR HCR H...

Страница 105: ...1 HOST FLAG 0 HOST RECEIVE DATA FULL HOST TRANSMIT DATA EMPTY HOST COMMAND PENDING HOST STATUS REGISTER HSR READ ONLY DMA 0 X FFEB X FFEB RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE TRANSMI...

Страница 106: ...is set When HRIE is cleared HRDF interrupts are disabled When HRIE is set a host receive data interrupt request will occur if HRDF is also set Hardware and software resets clear HRIE 5 3 2 1 2 HCR Ho...

Страница 107: ...st Status Register HSR The HSR is an 8 bit read only status register used by the DSP to interrogate status and flags of the HI It can not be directly accessed by the host processor When the HSR is rea...

Страница 108: ...soft ware individual and STOP resets clear HF0 5 3 2 2 5 HSR Host Flag 1 HF1 Bit 4 The HF1 bit in the HSR indicates the state of host flag 1 in the ICR on the host processor side HF1 can only be chang...

Страница 109: ...reg ister contains valid data when the HRDF bit is set Reading HRX clears HRDF The DSP may program the HRIE bit to cause a host receive data interrupt when HRDF is set Resets do not affect HRX 5 3 2 4...

Страница 110: ...nterrupt service routine must read or write the appropriate HI register clearing HRDF or HTDE for example to clear the interrupt In the case of host command interrupts the interrupt acknowledge from t...

Страница 111: ...erations Host Side for additional information 5 3 3 Host Interface Host Processor Viewpoint The HI appears to the host processor as eight words of byte wide static memory The host may access the HI as...

Страница 112: ...the DSP interrupt response is sufficiently fast most host micro processors can load or store data at their maximum programmed I O non DMA instruction rate without testing the handshake flags for each...

Страница 113: ...s are reset values HM1 0 HM0 0 INIT 0 MODES 0 0 Interrupt Mode DMA Off 0 1 24 Bit DMA Mode 1 0 16 Bit DMA Mode 1 1 8 Bit DMA Mode 0 HOST VECTOR 12 7 5 0 COMMAND VECTOR REGISTER CVR READ WRITE HC 0 1 H...

Страница 114: ...uest Enable TREQ Bit 1 The TREQ bit is used to control the HREQ pin for host transmit data transfers In interrupt mode DMA off TREQ is used to enable interrupt requests via the external HREQ pin when...

Страница 115: ...cessor and cannot be changed by the DSP Hardware software individual and STOP resets clear HF1 5 3 3 2 6 ICR Host Mode Control HM1 and HM0 bits Bits 5 and 6 The HM0 and HM1 bits select the transfer mo...

Страница 116: ...er on the host data bus the address counter is incremented to the next register When the address counter reaches the highest register RXL or TXL the address counter is not incremented but is loaded wi...

Страница 117: ...OST INTERFACE HI MOTOROLA PORT B 5 25 transferring only part of the first data word Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com n...

Страница 118: ...ways loads the DMA address counter and clears the channel according to TREQ and RREQ INIT execution is not affected by HM1 and HM0 The internal DMA counter is incremented with each DMA transfer each H...

Страница 119: ...gure 5 14 5 3 3 3 1 CVR Host Vector HV Bits 0 5 The six HV bits select the host command exception address to be used by the host com mand exception logic When the host command exception is recognized...

Страница 120: ...e HC and HV in the same write cycle if desired Hardware software individual and STOP resets clear HC 5 3 3 4 Interrupt Status Register ISR The ISR is an 8 bit read only status register used by the hos...

Страница 121: ...ates thatboth the TXH TXM TXL and the HRX registers are empty TRDY TXDE HRDF When TRDY is set to one the data that the host processor writes to TXH TXM and TXL will be immediately transferred to the D...

Страница 122: ...indicated by the ISR RXDF and TXDE status bits respectively If the interrupt source has been enabled by the associated request enable bit in the ICR HREQ will be set if one or more of the two enabled...

Страница 123: ...y order to transfer 8 16 or 24 bit data However writing TXL clears the TXDE bit Because writing the TXL register clears the TXDE status bit TXL is normally the last register written during a 16 or 24...

Страница 124: ...pins are configured as GPIO input pins during hardware reset Register Name Register Data Reset Type HW Reset SW Reset IR Reset ST Reset ICR INIT 0 0 0 0 HM 1 0 0 0 0 0 TREQ 0 0 0 0 RREQ 0 0 0 0 HF 1 0...

Страница 125: ...en the host interface is not being used and is config ured as a GPIO input pin during hardware reset 5 3 4 5 Host Request HREQ This open drain output signal is used by the DSP56002 HI to request servi...

Страница 126: ...Figure 5 16 In this case all other HI control pins are ignored and the state of the HI is not affected Note HACK should always be pulled high when it is not in use 5 3 5 Servicing the Host Interface...

Страница 127: ...6002 Technical Data Sheet 5 3 5 2 HI Interrupts Host Request HREQ The host processor interrupts are external and use the HREQ pin HREQ is normally con nected to the host processor maskable interrupt I...

Страница 128: ...TRDY 1 signifying the transmit data register is empty and that the receive data register on the DSP CPU side is also empty so that the data written by the host processor will be transferred directly t...

Страница 129: ...quest is cleared or masked In the case where the host processor is a member of the MC680XX Family servicing the interrupt will start by asserting HREQ to interrupt the processor see Figure 5 17 The ho...

Страница 130: ...6 HI Application Examples 5 3 6 HI Application Examples The following paragraphs describe examples of initializing the HI transferring data with the HI bootstrapping via the HI and performing DMA tra...

Страница 131: ...m programmed I O non DMA instruction rate without testing the handshake flags for each transfer If the full handshake is not needed the host processor can treat the DSP as fast memory and data can be...

Страница 132: ...BLE HOST COMMAND PENDING INTERRUPT ENABLE INTERRUPT BIT 2 1 DISABLE INTERRUPT BIT 2 0 4 SET CLEAR HOST FLAG 2 OPTIONAL ENABLE FLAG BIT 3 1 DISABLE FLAG BIT 3 0 5 SET CLEAR HOST FLAG 3 OPTIONAL ENABLE...

Страница 133: ...from the host processor to the DSP are STEP 2 OF HOST PORT CONFIGURATION 1 CLEAR HOST COMMAND BIT HC BIT 7 0 1 7 6 5 0 HC HV 2 OPTION 1 SELECT HOST VECTOR HV OPTIONAL SINCE HV CAN BE SET ANY TIME BEFO...

Страница 134: ...6 From the DSP s viewpoint the HRDF bit when set in the HSR indicates that data is waiting in the HI for the DSP INIT HM1 HM0 HF1 HF0 TREQ RREQ 0 Reserved write as zero 7 6 5 4 3 2 1 0 INITIALIZE DSP...

Страница 135: ...ares the DSP CPU to look for the host flag HF0 1 The JCLR instruction is a polling loop that looks for HF0 1 which indicates that the host processor is ready When the host processor is ready to transf...

Страница 136: ...addition the HC can cause any of the other 19 interrupt routines in the DSP to be executed The process to execute a HC see Figure 5 28 is as follows TREQ RREQ INIT Execution 0 0 INIT 0 Address Counter...

Страница 137: ...STATUS REGISTER HSR READ ONLY HRDF HOST RECEIVE DATA FULL 1 THE HOST RECEIVE REGISTER HRX CONTAINS DATA FROM THE HOST PROCESSOR 0 HRX IS EMPTY DMA INDICATES THE HOST PROCESSOR HAS ENABLED THE DMA MOD...

Страница 138: ...RANSMIT BYTE REGISTERS WRITE TO TXL CLEARS TXDE IN ISR 6 IF DSP560022 HAS OLD DATA IN HRX THEN HRDF 1 TXH TXM TXL 7 0 5 6 LAST WRITE 7 TRANSMIT BYTE REGISTERS TBR 7 WHEN DSP56002 READS HRX THEN HRDF 0...

Страница 139: ...IDLE LINE 001C SCI TIMER 001E RESERVED 0020 HOST RECEIVE DATA 0022 HOST TRANSMIT DATA 0024 HOST COMMAND DEFAULT 0026 AVAILABLE FOR HOST COMMAND 0028 AVAILABLE FOR HOST COMMAND 003C AVAILABLE FOR HOST...

Страница 140: ...ND IS MASKED UNTIL HCIE 1 5 WHEN THE HOST COMMAND EXCEPTION IS ACKNOWLEDGED THE HC BIT IS CLEARED BY THE HOST COMMAND LOGIC HC CAN BE READ AS A STATUS BIT HCP HOST COMMAND PENDING EXCEPTION VECTOR TAB...

Страница 141: ...is accepted Although the HV can be programmed to any exception vector it is not recommended that HV 0 RESET be used because it does not reset the DSP hardware DMA must be disabled to use the host exc...

Страница 142: ...is so fast host handshaking is generally not required Figure 5 29 Bootstrap Using the HI DSP56002 HR W HEN H0 H7 F32 F32 F32 F32 LS09 ADDRESS DECODE 1K 5 V HA0 HA2 LDS AS DTACK A1 A3 D0 D7 R W A4 A23...

Страница 143: ...or needs to terminate the bootstrap loading before 512 words have been down loaded it can set the HF0 bit in the ICR The DSP will then terminate the down load and start executing at location P 0000 Si...

Страница 144: ...ill be transferred to the receive byte registers RXH RXM RXL This transfer sets RXDF in the ISR 7 which the host processor can poll to see if data is available or if the RREQ bit in the ICR is set the...

Страница 145: ...T CONTROL REGISTER HCR READ WRITE HTIE HOST TRANSMIT INTERRUPT ENABLE 1 ENABLE THE DSP INTERRUPT TO P 0022 0 DISABLE THE DSP INTERRUPT TO P 0022 DSP INTERRUPT IS CAUSED BY HTDE 1 INIT HM1 HM0 HF1 HF0...

Страница 146: ...HTDE 0 THEN TRANSFER OCCURS RXH RXM RXL 7 0 5 6 LAST READ 7 RECEIVE BYTE REGISTERS RBR HREQ DMA 0 HF3 HF2 TRDY TXDE 1 2 7 0 INTERRUPT ST A TUS REGISTER ISR RXDF RECEIVE DATA FULL INIT HM1 HM0 HF1 HF0...

Страница 147: ...g any of the MAIN PROGRAM transmit 24 bit data to host ORG P 40 MOVEP 1 X PBC Turn on Host Port MOVEP 0C00 X IPR Turn on host interrupt MOVEP 0 X HCR Turn off XMT and RCV interrupts MOVE 0 SR Unmask i...

Страница 148: ...N and HA0 HA2 to transfer data The host can therefore transfer data in the other direction during the DMA operation using polling techniques 5 V DMA CONTROLLER TRANSFER REQUEST TRANSFER ACKNOWLEDGE DS...

Страница 149: ...contents of TXH TXM TXL are transferred to HRX provided HRDF 0 After the transfer to HRX TXDE will be set to one and HREQ will be asserted to start the transfer of another word from external memory t...

Страница 150: ...sfer see Figure 5 39 HREQ DMA 0 HF3 HF2 TRDY TXDE RXDF 2 7 0 INTERRUPTST A TUS REGISTER ISR READONL Y 0 0 Interrupt Mode DMA Off 0 1 24 Bit DMA Mode 1 0 16 Bit DMA Mode 1 1 8 Bit DMA Mode INIT HM1 HM0...

Страница 151: ...FACE MODE 24 BIT DMA HOST TO DSP USE INIT BIT TO SET TXDE CLEAR HRDF LOAD DMA COUNTER 3 TELL DSP56002 WHERE TO STORE DATA i e PROGRAM ADDRESS REGISTER R7 ENABLE INTERRUPT HRIE CAN BE DONE WITH A HOST...

Страница 152: ...y clearing the HM1 and HM0 bits and clearing TREQ The HREQ will be active immediately after initialization is completed depending on hard ware because the data direction is host to DSP and TXH TXM and...

Страница 153: ...rd size HM0 and HM1 the direction TREQ 0 RREQ 1 and setting INIT 1 see Figure 5 40 for additional information on these bits 3 Initialize the DSP s source pointer 3 used in the DMA exception handler an...

Страница 154: ...AD DMA COUNTER 5 HOST IS FREE TO PERFORM OTHER TASKS i e DSP TO HOST TRANSFER ON A POLLED BASIS 8 TERMINATE DMA CHANNEL 9 TERMINATE DSP DMA MODE BY CLEARING HM1 HM0 AND TREQ 7 DMA CONTROLLER INTERRUPT...

Страница 155: ...r multiple bytes If an MC68020 or MC68030 is used dynamic bus siz ing can be used to transfer multiple bytes with any instruction Figure 5 43 is a high level block diagram of a system using a single h...

Страница 156: ...REQ HEN HACK HR W HA0 HA2 H0 H7 ADDRESS DECODE INTERRUPT VECTOR DECODE MC68000 USE MOVEP for multiple byte transfers MC68020 or MC68030 Any Memory references will work due to dynamic bus sizing INTERR...

Страница 157: ...HOST SSI DSP56002 HOST SSI DSP56002 HOST SSI DSP56002 HOST CODEC CODEC ANALOG OUTPUT ANALOG INPUT ANALOG OUTPUT REQ RD WR ADDRESS BUS DATA BUS SELECT SELECT SELECT RX TX RX TX RX TX RX Figure 5 43 Mu...

Страница 158: ...the clock rate used by the DSP but there is a chance that the state of the bit could be changing during the read operation This possible change is generally not a system problem since the bit will be...

Страница 159: ...time the HC bit is cleared However the HV can be changed when the HC bit is set 6 When using the HREQ pin for handshaking wait until HREQ is asserted and then start writing reading data using the HEN...

Страница 160: ...HOST INTERFACE HI 5 68 PORT B MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 161: ...MOTOROLA 6 1 SECTION 6 PORT C Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 162: ...CTION 6 3 6 2 GENERAL PURPOSE I O PORT C 6 4 6 3 SERIAL COMMUNICATION INTERFACE SCI 6 11 6 4 SYNCHRONOUS SERIAL INTERFACE SSI 6 76 Freescale Semiconductor I Freescale Semiconductor Inc For More Inform...

Страница 163: ...ecs digital to analog and analog to digital converters and any of several transducers This section describes all three port C functions as well as examples of how to configure and use each function EX...

Страница 164: ...y setting the appropriate PCC bit memory location X FFE1 to zero for general purpose I O or to one for serial interface The PCDDR memory location X FFE3 programs each pin corresponding to a bit in the...

Страница 165: ...output If the PCD DR is set configured as an output for a given serial interface pin when the processor reads the PCD it sees the contents of the PCD rather than the logic level on the pin another ca...

Страница 166: ...data to from a peripheral to memory and execute one other instruction or to move the data to an absolute address MOVEP is the only memory to memory move instruction however one of the operands must b...

Страница 167: ...f steps 1 2 and 3 in Figure 6 7 is optional and can be changed as needed 6 2 2 Port C General Purpose I O Timing Parallel data written to Port C is delayed by one instruction cycle For example the fol...

Страница 168: ...TA REGISTER SRX STX SCI MID REC XMIT DATA REGISTER SRX STX SCI LOW REC XMIT DATA REGISTER SRX STX SCI TRANSMIT DATA ADDRESS REGISTER STXA SCI CONTROL REGISTER SCCR SCI INTERFACE STATUS REGISTER SSR SC...

Страница 169: ...er allowing the address space to be extended from 64K words 16 bits to 33 5 million words CC 1 CD 0 CD 1 CD 2 CD 3 CD 4 CD 5 CD 6 CD 7 CD 8 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PC 8 STEP 1 SELECT E...

Страница 170: ...Therefore if wait states are inserted in the DSP CPU timing they also affect Port C timing As a result Port A and Port C in the previous synchronization example will always stay synchronized regardle...

Страница 171: ...rupt vector have been in cluded so that the baud rate generator can function as a general purpose timer when it is not being used by the SCI peripheral or when the interrupt timing is the same as that...

Страница 172: ...s not being used 6 3 1 3 SCI Serial Clock SCLK This bidirectional pin provides an input or output clock from which the transmit and or re ceive baud rate is derived in the asynchronous mode and from w...

Страница 173: ...TDRE TRNE 0 0 0 0 0 0 1 1 SCI ST A TUS REGISTER SSR READ ONL Y RECEIVED BIT 8 FRAMING ERROR FLAG PARITY ERROR FLAG OVERRUN ERROR FLAG TRANSMITTER EMPTY TRANSMITTER DATA REGISTER EMPTY RECEIVE DATA RE...

Страница 174: ...X FFF5 X FFF4 SRX SRX SRX SCI RECIEVE DATA REGISTER HIGH READ ONLY SCI RECIEVE DATA REGISTER MID READ ONLY SCI RECEIVE DATA REGISTER LOW READ ONLY RXD SCI RECEIVE DATA SHIFT REGISTER NOTE SRX is the...

Страница 175: ...an odd number the parity bit is made equal to one and thus produces an odd number If the receiver counts an even number of ones an error in transmission has occurred When even parity is selected an e...

Страница 176: ...YPE STOP BIT EVEN PARITY MODE 5 2 1 0 1 0 1 WDS2 WDS1 WDS0 X FFF0 11 BIT ASYNCHRONOUS 1 START 8 DATA 1 ODD PARITY 1 STOP TX SSFTD 0 D0 D1 D2 D3 D4 D5 D6 START BIT D7 OR DATA TYPE STOP BIT ODD PARITY M...

Страница 177: ...ITY MODE 5 2 1 0 1 0 1 WDS2 WDS1 WDS0 X FFF0 11 BIT ASYNCHRONOUS 1 START 8 DATA 1 ODD PARITY 1 STOP TX SSFTD 1 START BIT D7 OR DATA TYPE STOP BIT ODD PARITY MODE 6 2 1 0 1 1 0 WDS2 WDS1 WDS0 X FFF0 11...

Страница 178: ...re enabled by an idle string of at least 10 or 11 depending on WDS mode consecutive ones The transmitter s software must provide this idle string between consecutive messages The idle string cannot oc...

Страница 179: ...rdware and software reset RWU is a don t care in the synchronous mode 6 3 2 1 6 SCR Wired OR Mode Select WOMS Bit 7 When the WOMS bit is set the SCI TXD driver is programmed to function as an open dra...

Страница 180: ...nd message to STX In this sequence if the first byte of the second message is not transferred to the STX prior to the finish of the preamble transmission then the transmit data line will simply mark i...

Страница 181: ...ta interrupt from the inter rupt controller TIE is cleared by hardware and software reset 6 3 2 1 12 SCR Timer Interrupt Enable TMIE Bit 13 The TMIE bit is used to enable the SCI timer interrupt If TM...

Страница 182: ...the transmitter When TRNE is set data written to one of the three STX locations or to the STXA will be transferred to the transmit shift register and be the first data transmitted TRNE is cleared when...

Страница 183: ...ransition of IDLE from zero to one can cause an IDLE interrupt ILIE IDLE is cleared by the hard ware software SCI individual and stop reset 6 3 2 2 5 SSR Overrun Error Flag OR Bit 4 The OR flag is set...

Страница 184: ...re software SCI individual and stop reset clear R8 6 3 2 3 SCI Clock Control Register SCCR The SCCR is a 16 bit read write register which controls the selection of the clock modes and baud rates for t...

Страница 185: ...he transmitter and receiver are synchronous with each other 6 3 2 3 1 SCCR Clock Divider CD11 CD0 Bits 11 0 The clock divider bits CD11 CD0 are used to preset a 12 bit counter which is decre mented at...

Страница 186: ...M selects internal or external clock for the receiver see Figure 6 35 RCM equals zero selects the internal clock RCM equals one selects the external clock from the SCLK pin Hardware and software reset...

Страница 187: ...zeroed Mapping SRX as described allows three bytes to be efficiently packed into TCM RCM TX Clock RX Clock SCLK Pin Mode 0 0 Internal Internal Output Synchronous Asynchronous 0 1 Internal External Inp...

Страница 188: ...at order for SSFTD equals zero see Figure 6 10 a For SSFTD equals one the data bits are transmitted MSB first see Figure 6 10 b The clock source is de fined by the receive clock mode RCM select bit in...

Страница 189: ...er there will be a two to four serial clock cycle delay between when the data is transferred from either STX or STXA to the transmit shift register and when the first bit appears on the TXD pin A seri...

Страница 190: ...ength and format of the serial word is defined by the WDS0 WDS1 and WDS2 control bits in the SCR In the asynchronous modes the start bit the eight data bits with the LSB first if SSFTD 0 and the MSB f...

Страница 191: ...or software reset 2 Program SCI control registers 3 Configure SCI pins at least one as not general purpose I O Figure 6 14 and Figure 6 15 show how to configure the bits in the SCI registers Figure 6...

Страница 192: ...0 COD 12 0 0 CD 11 0 11 0 0 0 SRX SRX 23 0 23 16 15 8 7 0 STX STX 23 0 23 0 SRSH SRS 8 0 8 0 STSH STS 8 0 8 0 NOTES SRSH SCI receive shift register STSH SCI transmit shift register HW Hardware reset...

Страница 193: ...al clock to the SCI For example a 2 048 MHz bit rate requires a CPU clock of 32 768 MHz An application may need a 40 MHz CPU clock and an external clock for the SCI 1 PERFORM HARDWARE OR SOFTWARE RESE...

Страница 194: ...BIT MULTIDROP 1 START 8 DATA EVEN PARITY 1 STOP 111 RESERVED STEP 2a SELECT SCI OPERATION FOR A BASIC CONFIGURATION SET SCKP BIT 15 0 STIR BIT 14 0 TMIE BIT 13 0 ILIE BIT 10 0 RWU BIT 6 0 WAKE BIT 5 0...

Страница 195: ...CLOCK PRESCALER BIT SCP BIT 13 ACCORDING TO TABLES 11 2 OR 11 3 SET TRANSMIT CLOCK SOURCE EXTERNAL CLOCK 1 INTERNAL CLOCK 0 SET RECEIVE CLOCK SOURCE EXTERNAL CLOCK 1 INTERNAL CLOCK 0 SET SCI CLOCK PRE...

Страница 196: ...a Asynchronous SCI Bit Rates for a 40 MHz Crystal Bit Rate BPS SCP Bit Divider Bits CD0 CD11 Crystal Frequency 9600 0 040 39 936 000 4800 0 081 39 936 000 2400 0 103 39 936 000 1200 0 207 39 936 000...

Страница 197: ...096M 0 000 0 128K 0 01F 0 64K 0 03F 0 56K 0 048 0 195 32K 0 07F 0 16K 0 0FF 0 8000 0 1FF 0 4000 0 3FF 0 2000 0 7FF 0 1000 0 FFF 0 Table 6 4 a Synchronous SCI Bit Rates for a 32 768 MHz Crystal BPS f0...

Страница 198: ...NSMIT DATA 001A SCI IDLE LINE 001C SCI TIMER 001E RESERVED 0020 HOST RECEIVE DATA 0022 HOST TRANSMIT DATA 0024 HOST COMMAND DEFAULT 0026 AVAILABLE FOR HOST COMMAND 0028 AVAILABLE FOR HOST COMMAND 003A...

Страница 199: ...mode 0 buses as both a controller master or a peripheral slave and is compatible with the SSI mode if SCKP equals one In synchronous mode the clock is always common to the transmit and receive shift r...

Страница 200: ...CI CLOCK CONTROL REGISTER SCCR READ WRITE 0 TCM RCM CLOCK OUTPUT SCP 0 B0 B1 B2 B3 B4 B5 B6 B7 TRANSMIT DATA SSFTD 0 XXXXXX XX XX XX XX XX XX XX XXXXXXX RECEIVE DATA WRITE STX 0 1 2 3 4 5 6 7 SAMPLE E...

Страница 201: ...ons two devices transmitting simultaneously must be avoid ed with this circuit by using a protocol such as alternating transmit and receive periods In the example the 8051 is the master device because...

Страница 202: ...CD2 CD1 CD0 SCI CLOCK CONTROL REGISTER SCCR READ WRITE 1 TCM RCM CLOCK INPUT SKP 0 B0 B1 B2 B3 B4 B5 B6 B7 TRANSMIT DATA SSFTD 0 XXXXXX XX XX XX XX XX XX XX XXXXXXX RECEIVE DATA WRITE STX 0 1 2 3 4 5...

Страница 203: ...ND 2 TRDE TDRE 0 BY STX WRITE TXD TRANS MIT DATA BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 SECOND WORD SERIAL CLOCK EXT STX WRITE RANGE FIRST WORD NOTE In external clock mode i...

Страница 204: ...embedded word sync which allows an un synchronized data clock to be synchronized with the word if the clock rate and number of bits per word is known Thus the clock can be generated by the receiver r...

Страница 205: ...it is enabled by 6 setting the RXD bit in the PCC The receiver is continually sampling RDX at the 16 clock rate to find the idle start bit transition edge When that edge is detected 1 the following ei...

Страница 206: ...TURN ON RECEIVER RE 1 4 OPTIONALLY ENABLE RECEIVER INTERRUPTS RIE 1 RIE RE 5 SET THE BAUD RATE BY PROGRAMMING THE SCCR CCx Function 0 GPIO 1 Serial Interface PRESCALER IF SCP 1 THEN DIVIDE BY 8 IF SCP...

Страница 207: ...TATUS REGISTER SSR READ ONLY 3 IF RIE 1 IN SCR THEN AN INTERRUPT IS GENERATED SCI RECEIVE DATA RECEIVE INTERRUPT SERVICE ROUTINE P 0014 INTERRUPT VECTOR TABLE 4 THE RECEIVE INTERRUPT SERVICE ROUTINE R...

Страница 208: ...enabled by 6 setting the TXD bit in the PCC Transmis sion begins with 7 a preamble of ones If polling is used to transmit data see Figure 6 26 the polling routine can look at either TDRE or TRNE to de...

Страница 209: ...R PE OR FE IN SSR 7 6 5 4 3 2 1 0 RDRF X FFF1 SCI STATUS REGISTER SSR READ ONLY SCI RECEIVE DATA RECEIVE WITH EXCEPTION INTERRUPT SERVICE ROUTINE P 0016 INTERRUPT VECTOR TABLE 5 READ SSR SERIAL STRING...

Страница 210: ...SMITTER SYSTEM CCx Function 0 GPIO 1 Serial Interface 7 THE TRANSMITTER WILL FIRST BROADCAST A PREAMBLE OF ONES BEFORE BEGINNING DATA TRANSMISSION 10 ONES WILL BE TRANSMITTED FOR THE 10 BIT ASYNCHRONO...

Страница 211: ...F TIE 1 IN SCR AND TDRE 1 IN SSR THEN AN INTERRUPT IS GENERATED TDRE 6 THE CHARACTER IN STX IS COPIED INTO TRANSMIT DATA SHIFT REGISTER TRNE IS CLEARED TDRE IS SET GO TO STEP 2 TRNE 23 16 15 8 7 0 X F...

Страница 212: ...TMIE TIE RIE ILIE TE RE WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0 SCI INTERFACE CONTROL REGISTER SCR READ WRITE STIR TOGGLE 1 0 1 TO SEND A CHARACTER TIME OF ALL ONES MARKS TOGGLE 0 1 0 TO SEND A CHARAC...

Страница 213: ...s dis abled until another byte is ready for transmission The SCI is initialized by setting the in terrupt level which configures the SCR and SCCR and then is enabled by writing the PCC The main progra...

Страница 214: ...TIALIZE THE SCI PORT AND RX TX BUFFER POINTERS ORG P START Start the program at location 40 ORI 03 MR Mask interrupts temporarily MOVEP C000 X IPR Set interrupt priority to 2 MOVEP 0B02 X SCR Disable...

Страница 215: ...The particular message format and protocol used are determined by the user s software These message formats include point to point bus token ring and custom configura tions The SCI multidrop network...

Страница 216: ...S 2 RXD MC68HC11 ADDRESS 3 RXD OTHER SERIAL DEVICE ADDRESS N TXD DSP56002 DEVICE RECEIVING MESSAGE RECEIVER INTERRUPT DOES HEADER EQUAL MY ADDRESS NO RECEIVE REST OF MESSAGE DO NOT MASK INTERRUPTS YES...

Страница 217: ...P from reading messages intended for other processors The usual operational procedure is for each DSP to suspend SCI reception the DSP can con tinue processing until the beginning of a message Each DS...

Страница 218: ...A REGISTER LOW WRITE ONLY X FFF3 23 16 15 8 7 0 X FFF6 X FFF5 X FFF4 STX STX STX TXD TXD STXA SCI TRANSMIT DATA SHIFT REGISTER 23 16 15 8 7 0 A 41 01000001 DATA ADDRESS SCI TRANSMIT DATA SHIFT REGISTE...

Страница 219: ...PORT ADDRESS 3 XMIT REC DSP56002 SCI PORT ADDRESS N 1 XMIT REC DSP56002 SCI PORT ADDRESS N XMIT REC A2 MESSAGE A A3 MESSAGE C A1 MESSAGE B ADDRESS CHARACTER WAKEUP AND OR INTERRUPT IDLE IDLE LINE WAK...

Страница 220: ...001A INTERRUPT VECTOR TABLE A1 MESSAGE A A2 MESSAGE B LINE IS IDLE FOR 10 OR 11 STOP BITS 1 RWU IS CLEARED THE RECEIVER IS ENABLED 2 IDLE IS SET IN SSR INDICATING THE LINE IS IDLE 3 AN INTERNAL FLAG...

Страница 221: ...wakeup and RWU must be set to put the SCI to sleep and enable the wakeup function RIE should be set if interrupts are to be used to receive data 1 When an address character ninth bit 1 is received the...

Страница 222: ...R READ ONLY SCI RECEIVE DATA P 0014 INTERRUPT VECTOR TABLE A1 MESSAGE A A2 MESSAGE B 1 WHEN ADDRESS CHARACTER IS RECEIVED THEN R8 1 IN SSR AND RWU IS CLEARED THE RECEIVER WAKES UP 2 IF RIE 1 IN SCR TH...

Страница 223: ...address or data If it is an ad dress it compares the address with its own If the addresses do not match the SCI is put back to sleep If the addresses match the SCI is left awake and control is returne...

Страница 224: ...rface control register SCCR EQU FFF2 SCI clock control register STXA EQU FFF3 SCI transmit address register SRX EQU FFF4 SCI receive register STX EQU FFF4 SCI transmit register BCR EQU FFFE Bus contro...

Страница 225: ...mode Rec wakeup mode 11 bit multidrop 1 start 8 data 1 data type 1 stop MOVEP 0000 X SCCR Use internal TX RX clocks 625K BPS at 40 MHz MOVEP 03 X PCC Select pins TXD and RXD for SCI INITIALIZE INTERRU...

Страница 226: ...to see if the TX buffer is full MOVE R1 fix tail pointer now that we ve used it MOVE R0 B by comparing the head and tail pointers CMP A B of the circular transmit buffer JEQ SND_BUF if equal transmit...

Страница 227: ...SUBROUTINE TO WRITE BUFFER TO SCI USING A LONG INTERRUPT TX MOVEP X R0 X STX Transmit a byte and increment the pointer MOVE R0 A Check to see if the TX buffer is empty MOVE R1 B CMP A B JNE END_TX If...

Страница 228: ...ogrammed as GPIO pins the transmit interrupts should be turned off TIE 0 Under individual reset TDRE will remain set and the timer will continuously generate interrupts Figure 6 35 shows that an exter...

Страница 229: ...BY 16 TRANSMIT CONTROL IF ASYNC THEN DIVIDE BY 16 IF SYNC THEN MASTER DIVIDE BY 2 SLAVE DIVIDE BY 1 RECEIVE CONTROL IF ASYNC THEN DIVIDE BY 16 IF SYNC THEN MASTER DIVIDE BY 2 SLAVE DIVIDE BY 1 PERIOD...

Страница 230: ...nt the timer interrupt counter NOP This timer routine is implemented as a fast interrupt INITIALIZE THE SCI PORT ORG P START Start the program at location 40 MOVE 0 R0 Initialize the timer interrupt c...

Страница 231: ...e program will begin loading in program memory and 4 loads the program First the SCI Control Register is set to 0302 see Figure 5 2 which enables the trans mitter and receiver and configures the SCI f...

Страница 232: ...es 1 These diodes must be Schottky diodes 2 All resistors are 15K unless noted otherwise 3 When in RESET IRQA IRQB and NMI must be deasserted by external peripherals SCLK RXD TXD 16xCLK Serial Bootstr...

Страница 233: ...he starting address JCLR 2 X SSR Wait for RDRF to go high MOVEP X SRXL A2 Put 8 bits in A2 JCLR 1 X SSR Wait for TDRE to go high MOVEP A2 X STXL echo the received byte REP 8 ASR A _LOOP6 MOVE A1 R0 st...

Страница 234: ...ng a single transmit receive line multidrop word format and wired OR The use of wired OR requires a pullup resistor as shown A protocol must be used to prevent collisions This scheme is physically the...

Страница 235: ...Multimaster System Example MC68HC11 MASTER RXD TXD PC2 MASTER RECEIVE MASTER TRANSMIT DSP56002 SLAVE RXD TXD PC2 DSP56002 SLAVE RXD TXD PC2 DSP56002 SLAVE RXD TXD PC2 Figure 6 40 Master Slave System E...

Страница 236: ...s of I O per frame in the network mode This mode is typically used in star or ring time division multiplex networks with other DSP56K processors and or codecs The clock can be programmed to be continu...

Страница 237: ...Six Pins STD SSI Transmit Data SRD SSI Receive Data SCK SSI Serial Clock SC0 Serial Control 0 defined by SSI mode SC1 Serial Control 1 defined by SSI mode SC2 Serial Control 2 defined by SSI mode On...

Страница 238: ...of SC0 SC1 SC2 and SCK in the various configurations The following paragraphs describe the uses of these pins for each of the SSI operating modes Figure 6 42 and Figure 6 43 show the internal clock p...

Страница 239: ...ernal Not Used FS External Not Used SC2 1 out SCD2 FST Internal FST Internal FS Internal FS Internal SCK 0 in TXC External TXC External XC External XC External SCK 1 out SCKD TXC Internal TXC Internal...

Страница 240: ...can be independent of and asynchronous to the DSP system clock it must exceed the minimum clock cycle time of 8T i e the sys tem clock frequency must be at least four times the external SSI clock freq...

Страница 241: ...VE CONTROL LOGIC TRANSMIT CONTROL LOGIC FSL0 FSL1 FSL0 FSL1 SYNC TYPE SYNC TYPE SYN 0 SYN 1 INTERNAL RX FRAME CLOCK SCD1 1 SYN 1 SCD1 0 SYN 0 SCD1 SC1 SCD2 SC2 INTERNAL TX FRAME CLOCK FLAG1 IN SYNC MO...

Страница 242: ...is the receiver frame sync I O For synchronous mode with continuous clock this pin is serial flag SC1 and operates like the previously described SC0 SC0 and SC1 are independent serial I O flags but m...

Страница 243: ...egisters are illustrated in Figure 6 44 and Figure 6 45 The following paragraphs give detailed descriptions and op erations of each of the bits in the SSI registers The SSI registers are not prefaced...

Страница 244: ...CEIVE DATA REGISTER FULL TRANSMIT DATA REGISTER EMPTY RECEIVER OVERRUN ERROR FLAG INPUT FLAGS TRANSMIT FRAME SYNC RECEIVE FRAME SYNC TRANSMITTER UNDERRUN ERROR FLAG TIE 0 OUTPUT FLAGS SERIAL CONTROL D...

Страница 245: ...12 BIT 8 BIT a Receive Registers for SHFD 0 STD X FFEF 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE SERIAL TRANSMIT DATA TX REGISTER WRITE ONLY SERIAL RECEIVE S...

Страница 246: ...e Registers for SHFD 1 STD X FFEF 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE SERIAL TRANSMIT DATA TX REGISTER READ ONLY SERIAL TRANSMIT SHIFT REGISTER 23 16 1...

Страница 247: ...536 MHz to be generated Hardware and software reset clear PM0 PM7 6 4 2 1 2 CRA Frame Rate Divider Control DC4 DC0 Bits 8 12 The DC4 DC0 bits control the divide ratio for the programmable frame rate d...

Страница 248: ...B controls the SSI multifunction pins SC2 SC1 and SC0 which can be used as clock inputs or outputs frame synchronization pins or serial I O flag pins The serial output flag control bits and the direct...

Страница 249: ...D0 6 4 2 2 4 CRB Serial Control 1 Direction SCD1 Bit 3 SCD1 controls the direction of the SC1 I O line When SCD1 is cleared SC1 is an input when SCD1 is set SC1 is an output see Tables Table 6 5 and T...

Страница 250: ...SC0 SC1 SC2 SCK SRD STD SCD0 SCD1 SCD2 SCKD DIRECTION CONTROLLED BY RECEIVE CLOCK FLAG 0 RECEIVE FRAME SYNC FLAG 1 TRANSMIT FRAME SYNC TX AND RX FRAME SYNC TRANSMIT CLOCK TX AND RX CLOCK SSI RECEIVE...

Страница 251: ...hether the receive and transmit functions of the SSI occur synchronously or asynchronously with respect to each other When SYN is cleared asynchronous mode is chosen and separate clock and frame sync...

Страница 252: ...is to clear TE and TIE after TDE equals one In the network mode the operation of clearing TE and setting it again will disable the transmitter after completing transmission of the current data word un...

Страница 253: ...E 0 See SECTION 7 PROCESSING STATES in the DSP56000 Family Manual for more in formation on exceptions 6 4 2 2 15 CRB SSI Receive Interrupt Enable RIE Bit 15 When RIE is set the DSP will be interrupted...

Страница 254: ...data when the receiver shift reg ister is transferred into the receive data register The IF1 bit is enabled only when SCD1 is cleared and SYN is set indicating that SC1 is an input and the synchronous...

Страница 255: ...the serial receive data register This indicates that the data word is from the first time slot in the frame If word wide receive frame sync is selected FSL1 0 this indicates that the frame sync was hi...

Страница 256: ...transmit data with exception status interrupt will be generated if a transmit interrupt occurs with TUE clear the transmit data without errors interrupt will be generated Hardware software SSI individ...

Страница 257: ...e data pin Data is shifted in by the selected internal external bit clock when the associated frame sync I O or gated clock is asserted Data is assumed to be received MSB first if SHFD equals zero and...

Страница 258: ...16 15 12 11 8 7 0 RX 24 BITS SHFD 0 RECEIVE SHIFT REGISTER a SHFD 0 SRD GDB 23 16 15 12 11 8 7 0 RX SHFD 1 RECEIVE SHIFT REGISTER b SHFD 1 Figure 6 47 Receive Data Path Freescale Semiconductor I Free...

Страница 259: ...0 TX TRANSMIT SHIFT REGISTER 23 16 15 8 7 0 12 11 16 BIT 12 BIT 8 BIT STD GDB TX 24 BITS SHFD 1 TRANSMIT SHIFT REGISTER a SHFD 0 b SHFD 1 Figure 6 48 Transmit Data Path Freescale Semiconductor I Free...

Страница 260: ...initions Table 6 12 and Table 6 13 completely describe the SSI operational modes and pin definitions Table 6 5 is a simplified version of these tables The operational modes are as follows 1 Continuous...

Страница 261: ...1 0 0 1 0 X X 1 2 4 RXC RXC FSR FST TXC TXC 1 0 0 0 0 X X X 4 4 RXC RXC FSR FST TXC TXC 1 0 1 0 X X X X 4 4 F0 F0 F1 F1 FS XC XC 1 0 0 1 1 X X 0 8 2 RXC RXC FSR FST TXC TXC 1 0 1 1 X X X 0 8 9 F0 F0 F...

Страница 262: ...XC 1 1 0 X X 0 1 0 8 5 RXC FST TXC 1 1 1 X X X 1 0 8 9 F0 F0 F1 F1 FS XC 0 1 0 X X 0 1 X 6 5 RXC FST TXC Table 6 13 Mode and Pin Definition Table Gated Clock DC4 DC0 0 means that bits DC4 0 DC3 0 DC2...

Страница 263: ...0 TFS 2 0 0 0 0 IF 1 0 0 1 0 0 0 0 RDR RDR 23 0 23 0 TDR TDR 23 0 23 0 RSR RDR 23 0 23 0 TSR RDR 23 0 23 0 Table 6 14 SSI Registers After Reset NOTES 1 RSR SSI receive shift register 2 TSR SSI transm...

Страница 264: ...CRB are not affected This procedure allows the DSP program to reset each interface separately from the other internal peripherals The DSP program must use an SSI reset when changing the MOD GCK SYN SC...

Страница 265: ...D GCK SYN FSL1 FSL0 SHFD OF1 OF0 PRESCALER IF PSR 1 THEN DIVIDE BY 8 IF PSR 0 THEN DIVIDE BY 1 DIVIDE BY 2 SSI BIT RATE CLOCK DC4 DC0 Word Transfer Rate See Note 1 Words Frame See Note 2 0 0 0 0 0 Con...

Страница 266: ...AME LENGTH 1 RX AND TX DIFFERENT LENGTH SHIFT DIRECTION 0 MSB FIRST 1 LSB FIRST CLOCK SOURCE DIRECTION 0 INPUT EXTERNAL 1 OUTPUT INTERNAL SERIAL CONTROL DIRECTION BITS 0 INPUT 1 OUTPUT TRANSMIT ENABLE...

Страница 267: ...bits should be set according to the application requirements Table 6 15 a and Table 6 15 b provide a convenient listing of PSR and PM0 PM7 set tings for the common data communication rates and the hi...

Страница 268: ...4M 0 00 Table 6 15 b SSI Bit Rates for a 39 936 MHz Crystal BPS fosc 4 7 PSR 1 PM 1 where fosc 40 MHz PSR 0 or 1 PM 0 to FFF BPS fosc 4 7 PSR 1 PM 1 where fosc 39 936 MHz PSR 0 or 1 PM 0 to FFF Bit Ra...

Страница 269: ...error has occurred ROE is cleared by first reading the SSISR and then reading RX 3 SSI Transmit Data occurs when the transmit interrupt is enabled the trans mit data register is empty and no transmit...

Страница 270: ...STATUS 0018 SCI TRANSMIT DATA 001A SCI IDLE LINE 001C SCI TIMER 001E RESERVED 0020 HOST RECEIVE DATA 0022 HOST TRANSMIT DATA 0024 HOST COMMAND DEFAULT 0026 AVAILABLE FOR HOST COMMAND 0028 AVAILABLE F...

Страница 271: ...NG INTERRUPT IS CLEARED BY READING RX TRANSMIT INTERRUPT SERVICE ROUTINE 1 INTERRUPT IS GENERATED WHEN TIE 1 TDF 1 AND TUE 0 2 PENDING INTERRUPT IS CLEARED BY WRITING TO TX OR TSR TRANSMIT WITH EXCEPT...

Страница 272: ...lave device always uses an external clock 6 4 7 1 Data Operation Formats The data operation formats available to the SSI are selected by setting or clearing control bits in the CRB These control bits...

Страница 273: ...he active clock transitions Although the word length frame sync is shown in Figure 6 58 a bit length frame sync can be used see Figure 6 59 In gated clock systems frame syn chronization is inherent in...

Страница 274: ...AND FLAGS SET RECEIVER INTERRUPT AND FLAGS SET NOTE Interrupts occur and data is transferred once per frame sync NETWORK MOD 1 SERIAL CLOCK FRAME SYNC TRANSMITTER INTERRUPTS AND FLAGS SET RECEIVER INT...

Страница 275: ...ode External Frame Sync 8 Bit 1 Word in Frame SLOT 0 SLOT 1 SLOT 1 SLOT 0 FRAME SYNC FSL0 0 FSL1 0 FRAME SYNC FSL0 0 FSL1 1 FLAGS DATA Figure 6 57 Network Mode External Frame Sync 8 Bit 2 Words in Fra...

Страница 276: ...ME SYNC SERIAL DATA DATA DATA NOTE Frame sync is required to tell when data is present SERIAL CLOCK SERIAL DATA NOTES 1 Word synchronization is inherent in the serial clock signal 2 Frame Sync generat...

Страница 277: ...3 Data and flags transition after external frame sync but not before the rising edge of the clock 0 DATA OUT FOR DC 0 OR NETWORK MODES DATA OUT FOR DC 0 DATA IN LATCHED INPUT FLAGS LATCHED DC 0 DC 0 D...

Страница 278: ...DC 0 DATA IN LATCHED INPUT FLAGS LATCHED DC 0 FRAME SYNC OUT FSL0 0 FSL1 1 OUTPUT FLAGS DC 0 DATA OUT DC 0 FRAME SYNC OUT FSL0 0 FSL1 0 OUTPUT FLAGS DC 0 7 6 0 Figure 6 60 Internally Generated Clock T...

Страница 279: ...OUT DC 0 7 6 0 t dhgc 5 ns INPUT FLAGS LATCHED NOTES 1 Output enabled on rising edge of first clock input 2 Output disabled on falling edge of last clock pulse 3 t dhgc is guaranteed by circuit desig...

Страница 280: ...ration both use the SCK pin SC0 and SC1 are designated as flags or can be used as general purpose parallel I O SC2 is not defined if it is an input SC2 is the transmit and receive frame sync if it is...

Страница 281: ...ME SYNC INTERNAL FRAME SYNC SC0 SCK EXTERNAL TRANSMIT CLOCK EXTERNAL RECEIVE CLOCK INTERNAL CLOCK SSI BIT CLOCK NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SYN...

Страница 282: ...onous Operation Figure 6 65 Gated Clock Asynchronous Operation STD SRD SCK TXC and RXC FLAG 0 FLAG 1 FSr and FSt SSI PC8 PC7 PC6 PC3 PC4 PC5 SC0 SC1 SC2 Figure 6 66 Continuous Clock Synchronous Operat...

Страница 283: ...nsmit ter can have either a bit long or word long frame sync signal format and the receiver can have the same or opposite format The selection is made by programming FSL0 and FSL1 in the CRB as shown...

Страница 284: ...receding the data DATA DATA SERIAL CLOCK TX FRAME SYNC MIXED FRAME LENGTH FSL1 0 FSL0 1 TX SERIAL DATA RX FRAME SYNC DATA DATA RX SERIAL DATA DATA DATA SERIAL CLOCK TX FRAME SYNC MIXED FRAME LENGTH FS...

Страница 285: ...LOCK CONTROL 0 CONTINUOUS CLOCK SYN SYNC ASYNC CONTROL 1 SYNCHRONOUS SCD2 SERIAL CONTROL 2 DIRECTION 1 OUTPUT SCKD CLOCK SOURCE DIRECTION 1 OUTPUT FSL0 FRAME SYNC LENGTH 0 SAME LENGTHS FSL1 FRAME SYNC...

Страница 286: ...SELECT 0 NORMAL GCK GATED CLOCK CONTROL 0 CONTINUOUS SYN SYNC ASYNC CONTROL 1 SYNCHRONOUS SCD2 SERIAL CONTROL 2 DIRECTION 1 OUTPUT SCKD CLOCK SOURCE DIRECTION 1 OUTPUT FSL0 FRAME SYNC LENGTH 0 DIFFER...

Страница 287: ...ve shift register LSB first and shifted out of the transmit shift register LSB first 6 4 7 2 Normal Mode Examples The normal SSI operating mode characteristically has one time slot per serial frame an...

Страница 288: ...SHIFT REGISTER RX 23 16 15 8 7 0 7 0 7 0 7 0 RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE 8 BIT 12 BIT 16 BIT 24 BIT STD X FFEF 23 16 15 8 7 0 7 0 7 0 7 0 RECEIVE HIGH BYTE RECEIVE MIDDLE B...

Страница 289: ...T MIDDLE BYTE TRANSMIT LOW BYTE 8 BIT 12 BIT 16 BIT 24 BIT SRD X FFEF 23 16 15 8 7 0 7 0 7 0 7 0 RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE 23 16 15 8 7 0 7 0 7 0 7 0 RECEIVE HIGH BYTE REC...

Страница 290: ...ly The transmit data output STD is three stated except during the data transmission peri od The optional frame sync output flag outputs and clock outputs are not three stated even if both receiver and...

Страница 291: ...usly reset At this point the SSI is ready to transmit except that the interrupt is masked because the MR was cleared on reset and Port C is still configured as general purpose I O Unmasking the interr...

Страница 292: ...to 4 MOVE 0 X0 Initialize channel flag for SSI flag MOVE X0 X FLG Start with right channel first Initialize SSI Port MOVEP 3000 X IPR Set interrupt priority register for SSI MOVEP 401F X CRA Set conti...

Страница 293: ...The DSP program has to read the data from RX before a new data word is transferred from the receive shift register otherwise the receiver overrun error will be set ROE 1 Figure 6 74 illustrates the p...

Страница 294: ...eft or right data buffer depending on the results of the test The RTI instruction then returns control to the main program which will wait for the next interrupt SSI and other I O EQUATES IPR EQU FFFF...

Страница 295: ...e in which the DSP would interface to a TDM codec network or a network of DSPs is compatible with Bell and CCITT PCM data operation for mats The DSP may be a master device see Figure 6 75 that control...

Страница 296: ...ade to see if it is the beginning of a frame If it is the beginning of a frame SLOTCT1 is cleared to start counting the time slots If it is not the beginning of a frame SLOTCT1 is incremented The next...

Страница 297: ...A TO TX WRITE DUMMY DATA TO TSR EXIT YES NO NO YES RECEIVER FULL INTERRUPT TEST FOR FRAME SYNC RFS 1 CLEAR SLOT NUMBER SLOTCT2 0 INCREMENT SLOT NUMBER SLOTCT2 SLOTCT2 1 IS DATA FOR ME SLOTCT2 MYSLOT K...

Страница 298: ...and WL0 In this example an 8 bit word length was chosen WL1 0 and WL0 0 2 The number of time slots is selected by setting DC4 DC0 Four time slots were chosen for this example DC4 DC0 03 3 The serial...

Страница 299: ...ONTROL 1 SYNCHRONOUS SCD2 SERIAL CONTROL 2 DIRECTION 1 OUTPUT MASTER 0 INPUT SLAVE SCKD CLOCK SOURCE DIRECTION 1 OUTPUT MASTER 0 INPUT SLAVE FLS0 FRAME SYNC LENGTH 0 0 TX RX SYNC SAME LENGTH FSL1 FRAM...

Страница 300: ...h new data for the next time slot Software can also write to TSR to prevent transmitting in the next time slot Failing to reload TX or writing to the TSR before the transmit shift register is finished...

Страница 301: ...ot is for the right channel If the current time slot is for the left channel the TSR is written which three states the output to allow another DSP to transmit the left channel during the time slot SSI...

Страница 302: ...n SSI port JMP Wait for interrupt MAIN INTERRUPT ROUTINE XMT JSET 0 X FLG LEFT Check user flag RIGHT BCLR 0 X CRB Clear SC0 indicating right channel data MOVEP X R0 X TX Move data to TX register MOVE...

Страница 303: ...ill be MOVE 3 M0 split between two buffers which are MOVE 3 M1 modulus 4 Initialize SSI Port MOVEP 3000 X IPR Set interrupt priority register for SSI MOVEP 4100 X CRA Set word length 16 bits MOVEP AB0...

Страница 304: ...t is enabled RIE 1 The second data word second time slot in the frame begins shifting in immediately after the transfer of the first data word to the RX The DSP program has to read the data from RX wh...

Страница 305: ...d as the on demand mode of the SSI because it is the only data driven mode of the SSI i e data is transferred whenever data is present see Figure 6 80 and Figure 6 81 STD and SCK from DSP1 are connect...

Страница 306: ...t after everything else is configured and the DSP is ready to receive interrupts 5 The network mode must be selected MOD 1 6 A gated clock GCK 1 is selected in this example A continuous clock exam ple...

Страница 307: ...OF0 MOD SSI MODE SELECT 1 NETWORK GCK GATED CLOCK CONTROL 1 GATED CL0CK SYN SYNC ASYNC CONTROL 0 ASYNCHRONOUS SCD0 SERIAL CONTROL 2 DIRECTION 0 INPUT SCKD CLOCK SOURCE DIRECTION 1 OUTPUT SSI CONTROL R...

Страница 308: ...the transmit shift register is empty The receive and transmit in terrupts function as usual using TDE and RDF however transmit and receive underruns are impossible for on demand transmission and are...

Страница 309: ...0 to two makes the buffer circular modulo 3 which saves the step of resetting the pointer each loop PC3 is con figured as a general purpose output for use as a scope sync and CRA and CRB are then init...

Страница 310: ...ransmit DC 330000 DC F00000 MAIN PROGRAM ORG P 40 MOVE 0 R0 Pointer to data buffer MOVE 2 M0 Length off buffer is 3 Figure 6 85 On Demand Mode Transmit Example Program Sheet 1 of 2 DSP56002 PC3 SC2 ST...

Страница 311: ...E3 JCLR 6 X SSISR TDE3 Wait for TDE 1 FSC JSET 5 X PCD FSC Wait for frame sync to go low NOTE State of frame sync is directly determined by reading PC5 BCLR 3 X PCD Set PC3 lo example external enable...

Страница 312: ...E 0 R0 Pointer to data buffer MOVE 2 M0 Length of buffer is 3 MOVEP 001F X CRA Set Word Length 8 CLK 5 12 32 MHz MOVEP 1E30 X CRB Enable receiver Mode On Demand gated clock on synchronous mode Word fr...

Страница 313: ...cts to enable the appropriate codec for I O This procedure allows the transmit lines to be ORed together The appropriate out put flag pin changes at the same time as the first bit of the transmit word...

Страница 314: ...flags are double buffered with transmit data 3 Output flags change when data is transferred from TX to the transmit data shift register 4 Initial flag outputs last flag output value 5 Data and flags...

Страница 315: ...XO DSP5002 SRD STD SCK SC0 SC1 MICROPHONE SPEAKER PHONE LINE INPUT PHONE LINE OUTPUT OUTPUT FLAG 1 OUTPUT FLAG 0 OF0 OF1 SPEAKER PHONE Figure 6 88 Output Flag Example NOTE SC0 and SC1 are output flag...

Страница 316: ...CLOCK SOURCE DIRECTION 1 OUTPUT SCD1 AND SCD0 SERIAL CONTROL 1 AND 0 DIRECTION 1 OUTPUT 0 1 FILTER 1 1 0 FILTER 2 TRANSMIT DATA B7 B6 B5 B4 B3 B2 B1 B0 OUTPUT FLAG VALID OUTPUT FLAG OF0 AND LF1 ARE C...

Страница 317: ...n provide Cascading DSPs in this manner is useful in several network topologies including star and ring networks RECEIVE CLOCK RECEIVE DATA B7 B6 B5 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 RDF TDE ROE TUE RFS...

Страница 318: ...ay which is applicable to matrix relaxation processing is shown in Figure 6 95 To simplify the drawing only the center DSP is connected in this illustration In use all DSPs would have four three state...

Страница 319: ...L CLOCK SERIAL SYNC DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 SERIAL DATA IN SERIAL DATA OUT Figure 6 92 SSI TDM Parallel DSP Network Freescale Semiconductor I Freesca...

Страница 320: ...C2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 Figure 6 93 SSI TDM Connected Parallel Processi...

Страница 321: ...02 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 SERIAL IN SERIAL OUT Figure 6 94 SSI TDM Serial Parallel Processing Array DSP5600...

Страница 322: ...2 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 Figure 6 95 SSI Parallel Process...

Страница 323: ...SC2 SERIAL DATA BUS SERIAL CLOCK DSP56002 STD SRD SCK SC2 DSP56002 STD SRD SCK SC2 DSP56002 STD SRD SCK SC2 SERIAL SYNC Figure 6 96 SSI TDM Bus DSP Network Freescale Semiconductor I Freescale Semicon...

Страница 324: ...D SRD SCK SC2 SC1 SC0 DSP56002 SLAVE 3 STD SRD SCK SC2 SC1 SC0 MASTER TRANSMIT MASTER RECEIVE MASTER CLOCK MASTER SYNC FLAG 1 FLAG 0 NOTE Flags can specify data types control address and data Figure 6...

Страница 325: ...MOTOROLA 7 1 SECTION 7 DSP56002 TIMER AND EVENT COUNTER Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 326: ...EGISTER TCR 7 4 7 4 TIMER CONTROL STATUS REGISTER TCSR 7 5 7 5 TIMER EVENT COUNTER MODES OF OPERATION 7 7 7 6 TIMER EVENT COUNTER BEHAVIOR DURING WAIT and STOP 7 16 7 7 OPERATING CONSIDERATIONS 7 17 7...

Страница 327: ...O pin becomes three stated To prevent undes ired spikes from occurring the TIO pin should be pulled up or down when it is not in use 7 2 TIMER EVENT COUNTER BLOCK DIAGRAM Figure 7 1 shows a block diag...

Страница 328: ...the timer is enabled TE 1 and the user program writes to the TCR the value is stored there and will be loaded into the counter after the counter has been decremented to zero and a new event occurs In...

Страница 329: ...terrupts are disabled Hardware and software resets clear TIE 7 4 3 Inverter INV Bit 2 The INV bit affects the polarity of the external signal coming in on the TIO input and the polarity of the output...

Страница 330: ...proper functionality the GPIO function is enabled only if TC2 TC0 are all 0 zero and the GPIO bit is set 7 4 5 General Purpose I O GPIO Bit 6 If the GPIO bit is set GPIO 1 and if TC2 TC0 are all zero...

Страница 331: ...utput pin TC2 TC0 are all zero and DIR 1 writing to the DO bit writes the data to the TIO pin However if the INV bit is set the data written to the TIO pin will be inverted When GPIO mode is disabled...

Страница 332: ...e 1 is defined by TC2 TC0 equal to 001 With the timer enabled TE 1 the counter is loaded with the value contained by the TCR The counter is decremented by a clock derived from the DSP s internal clock...

Страница 333: ...al Clock Output Toggle Enabled Timer Mode 2 is defined by TC2 TC0 equal to 010 With the timer enabled TE 1 the counter is loaded with the value contained by the TCR The counter is decremented by a clo...

Страница 334: ...nes the polarity of the TIO output Figure 7 7 illustrates Timer Mode 2 7 5 4 Timer Mode 4 Pulse Width Measurement Mode Timer Mode 4 is defined by TC2 TC0 equal 100 In this mode TIO acts as a gating si...

Страница 335: ...read the TCR which now represents the widths of the TIO pulse The process is repeated until the timer is disabled TE 0 The INV bit determines whether the counting is enabled when TIO is high INV 0 or...

Страница 336: ...e counter is loaded in the TCR The user s program can read the TCR and subtract consecutive values of the counter to determine the distance between TIO edges The counter is not stopped and it continue...

Страница 337: ...at any given moment At the tran sition following the point where the counter reaches 0 the TS bit in TCSR is set and if the TIE is set an interrupt is generated The counter will wrap around and the p...

Страница 338: ...the transitions of the signal coming in on the TIO input pin At the transition that occurs after the counter has reached 0 the TS bit in TCSR is set and if the TIE is set the timer generates an inter...

Страница 339: ...er clocks are active and the timer ac tivity continues undisturbed If the timer interrupt is enabled when the final event occurs an interrupt will be generated and serviced It is recommended that the...

Страница 340: ...he TCR is loaded with 0 and the counter contained a non zero value before the TCR was loaded then after the timer is enabled it will count 224 events generate an interrupt and then generate an interru...

Страница 341: ...ount is completed and then generate an interrupt for every new event 7 8 SOFTWARE EXAMPLES 7 8 1 General Purpose I O Input The following routine can be used to read the TIO input pin MOVEP 000040 X TC...

Страница 342: ...utput pin MOVEP 000140 X TCSR clear TC2 TC0 set GPIO and set DIR for GPIO output set TIO to 0 BSET DO X TCSR set TIO to 1 NOP TE TCR Write Preload N TIO Event Counter N FFFF 0 Interrupt First Event La...

Страница 343: ...rd timer mode with simultaneous GPIO The timer is used to activate an internal task after 65536 clocks at the end of the task the TIO pin is toggled to signal end of task ORG P 3C this is timer interr...

Страница 344: ...into the counter BSET IPL X IPR enable IPL for timer ANDI CF MR remove interrupt masking in status register BSET TE X TCSR timer enable application program task task instructions end_of_task TE TCR W...

Страница 345: ...interrupt ORG P MAIN_BODY MOVE PULSE_WIDTH r0 r0 points to start of table MOVE FF M0 modulo 100 to wrap around on end of table MOVEP 000026 X TCSR enable timer interrupts mode 4 and set INV to measure...

Страница 346: ...A X TCSR enable timer interrupts mode 5 BSET IPL X IPR enable IPL for timer ANDI CF MR remove interrupt masking in status register BSET TE X TCSR timer enable do other tasks measure MOVEP X TCR A read...

Страница 347: ...1010100011010101 1001011001110100 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 1000101010100100 010001010101...

Страница 348: ...SECTION CONTENTS A 2 BOOTSTRAP AND ROM CODE MOTOROLA A 1 INTRODUCTION A 3 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 349: ...is will terminate the boot strap loading operation and start executing the loaded program at location P 0 of the internal program RAM If MC MB MA 11x the program loads program RAM from the SCI interfa...

Страница 350: ...ister Low ORG PL 0 PL 0 bootstrap code starts at 0 START MOVE 0 R0 default P address where prog will begin loading JCLR 4 OMR EPROMLD If MC MB MA 0xx go load from EPROM JSET 1 OMR SCILD If MC MB MA 11...

Страница 351: ...ess of 2nd 32 word bootstrap ROM EXTC MOVEP C000 X SCCR Configure SCI Clock Control Reg MOVEP 7 X PCC Configure SCLK TXD and RXD _SCI1 DO 6 _LOOP6 get 3 bytes for number of program words and 3 bytes f...

Страница 352: ...ting mode to 0 and trigger an exit from bootstrap mode ANDI 0 CCR Clear CCR as if RESET to 0 Delay needed for Op Mode change JMP R1 Then go to starting Prog addr End of bootstrap code Number of progra...

Страница 353: ...egisters are grouped between the central processing module and each peripheral Each register includes the name address reset value and meaning of each bit The sheets provide room to write the value fo...

Страница 354: ...TERRUPT VECTOR ADDRESSES B 4 B 3 INSTRUCTIONS B 5 B 4 CENTRAL PROCESSOR B 10 B 5 GP I O B 14 B 6 HOST B 16 B 7 SCI B 21 B 8 SSI B 24 B 9 TIMER B 27 Freescale Semiconductor I Freescale Semiconductor In...

Страница 355: ...SCI CONTROL REGISTER SCCR SCI INTERFACE STATUS REGISTER SSR SCI INTERFACE CONTROL REGISTER SCR SSI RECIEVE TRANSMIT DATA REGISTER RX TX SSI STATUS TIME SLOT REGISTER SSISR TSR SSI CONTROL REGISTER B C...

Страница 356: ...ception Status 0018 0 2 SCI Transmit Data 001A 0 2 SCI Idle Line 001C 0 2 SCI Timer 001E 3 NMI 0020 0 2 Host Receive Data 0022 0 2 Host Transmit Data 0024 0 2 Host Command default 0026 0 2 Available f...

Страница 357: ...CHG n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D BCLR n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D BSET n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D BTST n X aa 1 e...

Страница 358: ...aa xxxx n X pp xxxx n Y ea xxxx n Y aa xxxx n Y pp xxxx n S xxxx JSET n X ea xxxx 2 6 jx n X aa xxxx n X pp xxxx n Y ea xxxx n Y aa xxxx n Y pp xxxx n S xxxx JSR xxx 1 ea 4 jx ea JSSET n X ea xxxx 2 6...

Страница 359: ...ea S2 D2 xxxxxx D1 S2 D2 A X ea X0 A B X ea X0 B Y memory data move Y ea D mv mv Y aa D S Y ea S Y aa xxxxxx D Register and Y memory S1 D1 Y ea D2 mv mv data move S1 D1 S2 Y ea S1 D1 xxxxxx D2 Y0 A A...

Страница 360: ...ea Y pp MPY S2 S1 D parallel move 1 mv 2 mv S1 S2 D parallel move S n D no parallel move 1 2 MPYR S2 S1 D parallel move 1 mv 2 mv S1 S2 D parallel move S n D no parallel move 1 2 NEG D parallel move 1...

Страница 361: ...D1 S2 D2 TFR S D parallel move 1 mv 2 mv TST S parallel move 1 mv 2 mv 0 WAIT 1 n a NOTATION denotes the bit is unaffected by the operation denotes the bit may be set according to the definition depen...

Страница 362: ...erved Trace Mode Double Precision Multiply Mode Loop Flag Reset 0300 DM S Mode Register MR Condition Code Register CCR Port A Bus Control Register BCR X FFFE Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3...

Страница 363: ...e 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 Reset 000000 CENTRAL PROCESSOR Register IPR 23 22 21 20 19 18 16 17 0 0 0 0 0 0 0 0 0 0 0 0 SSL1 SSL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SCL1 SCL0 Enabled...

Страница 364: ...m as zero Mode M M M Operating Mode C B A 0 0 0 0 Single Chip Mode 1 0 0 1 Bootstrap from EPROM 2 0 1 0 Normal Expanded Mode 3 0 1 1 Development Mode 4 1 0 0 Reserved 5 1 0 1 Bootstrap from Host 6 1 1...

Страница 365: ...0 0 Clock Out Enabled Full Strength Output Buffer 0 1 Clock Out Enabled 2 3 Strength Output Buffer 1 0 Clock Out Enabled 1 3 Strength Output Buffer 1 1 Clock Out Disabled XTAL Disable Bit XTLD 0 Enab...

Страница 366: ...00000 Port B Data Register PBD X FFE4 Read Write Reset 000000 0 0 Port B Data usually loaded by program Port B Data Direction Control 0 Input 1 Output Port B Reserved Program as zero Sheet 1 of 2 23 0...

Страница 367: ...CC2 CC1 CC0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 0 0 0 Port C Pin Control 0 General Purpose I O Pin 1 Peripheral Pin Reserved Program as zero Sheet...

Страница 368: ...Read Write Flags Reserved Program as zero 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Port B Control Register PBC X FFE0 Read Write Reset 000000 Port B 0 0 0 DSP SIDE 23 0...

Страница 369: ...ost Transmit Data Register HTX X FFEB Write Only Reset 000000 Host Transmit Data usually loaded by program 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE 15 14 13 12 11 1...

Страница 370: ...Bit DMA 10 16 Bit DMA 11 8 Bit DMA Receive Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 Host DSP 1 DSP Host 7 INIT 6 5 0 PROCESSOR SIDE Command Vector Register CVR 1 Rea...

Страница 371: ...er Full 0 Wait 1 Read 7 HREQ 6 5 0 PROCESSOR SIDE DMA TRDY Host Request 0 HREQ Deasserted1 HREQ Asserted Interrupt Vector Register IVR 3 Read Write Reset 0F 4 3 2 1 0 IV4 IV3 IV2 IV1 IV0 Exception vec...

Страница 372: ...7 0 RECEIVE MIDDLE BYTE RECEIVE LOW BYTE 7 0 7 0 NOT USED TRANSMIT HIGH BYTE Transmit Byte Registers 7 6 5 4 Write Only Reset 00 0 0 0 0 0 0 0 0 RECEIVE HIGH BYTE NOT USED 7 6 5 4 7 6 5 4 TRANSMIT LOW...

Страница 373: ...ed Or Mode Select 1 Multidrop 0 Point to Point Transmitter Enable 0 Transmitter disabled 1 Transmitter enabled Transmit Interrupt Enable 0 Transmit Interrupts disabled 1 Transmit Interrupts enabled Id...

Страница 374: ...for receiver 1 External clock from SCLK Transmitter Clock Mode Source 0 Internal clock for transmitter 1 External clock from SCLK SCI Status Register SSR Address X FFF1 Read Only Reset 000003 7 6 5 4...

Страница 375: ...gister decoded at three different addresses X0 A B C SCI Transmit Data Registers Address X FFF4 X FFF6 Read Write Reset xxxxxx SCI Receive Data Registers Address X FFF4 X FFF6 Read Write Reset xxxxxx...

Страница 376: ...24 Bits Word Frame Rate Divider Control 00000 1 11111 32 Port C Control Register PCC X FFE1 Read Write Reset 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 0 0 0 0 0 P...

Страница 377: ...e 1 Enable Receive Interrupt Enable 0 Disable 1 Enable Receive Enable 0 Disable 1 Enable Transmit Interrupt Enable 0 Disable 1 Enable Gated Clock Control 0 Continuous Clock1 Gated Clock Output Flag x...

Страница 378: ...ror Flag 0 OK 1 Error Transmit Data Register Empty 0 Wait 1 Write Transmit Frame Sync 0 Sync Inactive1 Sync Active Receive Data Register Full 0 Wait 1 Read Serial Input Flag 0 If SCD0 0 and SYN 1 latc...

Страница 379: ...1 Output Internal Timer Pulse 0 1 0 Output Internal Timer Toggle 0 1 1 X X Undefined 1 0 0 Input Internal Input Width 1 0 1 Input Internal Input Period 1 1 0 Input External Standard Time Counter 1 1 1...

Страница 380: ......

Страница 381: ...MOTOROLA INDEX 1 INDEX Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 382: ......

Страница 383: ...2 frame rate divider control DC0 DC4 6 87 CRB 6 88 bit 0 serial output flag 0 OF0 6 88 bit 1 serial output flag 1 OF1 6 88 bit 10 gated control clock GCK 6 91 bit 11 mode select MOD 6 92 bit 12 transm...

Страница 384: ...st transmit interrupt enable HTIE 5 14 bit 2 host command interrupt enable HCIE 5 14 bit 3 host flag 2 HF2 5 14 bit 4 host flag 3 HF3 5 15 bits 5 6 7 reserved 5 15 HEN 2 9 5 32 HF0 5 16 5 19 5 23 read...

Страница 385: ...lize bit INIT 5 24 IDLE 6 23 IF0 6 94 IF1 6 94 ILIE 6 20 6 39 INIT 5 24 Instruction Set Summary B 5 Internal Processing DSP to host 5 59 host to DSP 5 56 INterrupt Sources B 4 Interrupt host command 5...

Страница 386: ...de 6 bootstrap from SCI 3 12 mode 7 reserved mode 3 12 setting changing 3 7 summary 3 8 OR 6 23 P PBC 5 4 PBD 5 4 PBDDR 5 4 PCAP 2 13 PCC 6 4 PCD 6 4 PCDDR 6 4 PE 6 23 PEN 2 14 Peripheral Memory Map B...

Страница 387: ...cc 2 13 R R8 6 24 RCM 6 26 RD 2 5 RDF 6 97 RDRF 6 23 RE 6 92 Receive Byte Registers RXH RXM RXL 5 29 B 20 Reset register contents and 5 17 RESET Pin 2 7 RFS 6 95 RIE 6 21 6 37 6 39 6 93 ROE 6 96 RREQ...

Страница 388: ...examples 6 127 normal network 6 112 on demand mode examples 6 145 SSI Pins 2 10 6 78 serial clock SCK 6 80 serial clock zero SC0 2 10 serial control SC0 6 82 serial control SC1 6 82 serial control SC2...

Страница 389: ...xample 7 21 Mode 5 7 12 Mode 5 Example 7 22 Mode 6 7 13 Mode 7 7 15 Operating Considerations 7 17 Period Measurement Mode 7 12 7 15 7 16 Programming Model 7 4 PWM Mode 7 11 7 13 7 14 Timer Control Sta...

Страница 390: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 391: ...use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life Buyer agrees to notify Motorola of any such intended end use whe...

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