Freescale Semiconductor DSP56002, Руководство пользователя

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PORT A TIMING
MOTOROLA PORT A 4 - 11
is enabled by read enable (RD) or write enable (WR). RD or WR is asserted to
“qualify” the address and memory reference signals as stable and to perform
the read or write data transfer. RD and WR are asserted in the second phase
of the bus cycle (if there are no wait states). Read enable is typically con-
nected to the output enable (OE) of the memory chips and simply controls the
output buffers of the chip-selected memory. Write enable is connected to the
write enable (WE) or write strobe (WS) of the memory chips and is the pulse
that strobes data into the selected memory. For a read operation, RD is
asserted and WR remains deasserted. Since write enable remains negated, a
memory read operation is performed. The DSP data bus becomes an input,
and the memory data bus becomes an output. For a write operation, WR is
asserted and RD remains deasserted. Since read enable remains deasserted,
the memory chip outputs remain in the high-impedance state even before write
strobe is asserted. This state assures that the DSP and the chip-selected
memory chips are not enabled onto the bus at the same time. The DSP data
bus becomes an output, and the memory data bus becomes an input.
3. Wait states are inserted into the bus cycle by a wait-state counter or by assert-
ing WT. The wait-state counter is loaded from the bus control register. If the
value loaded into the wait-state counter is zero, no wait states are inserted into
the bus cycle, and RD and WR are asserted as shown in Figure 4-6. If a value
W
≠
0 is loaded into the wait state counter, W wait states are inserted into the
bus cycle. When wait states are inserted into an external write cycle, WR is
delayed from T1 to T2. The timing for the case of two wait states (W=2) is
shown in Figure 4-7.
4. When RD or WR are deasserted at the start of T3 in a bus cycle, the data is
latched in the destination device – i.e., when RD is deasserted, the DSP
latches the data internally; when WR is deasserted, the external memory
latches the data on the positive-going edge. The address signals remain sta-
ble until the first phase of the next external bus cycle to minimize power dissi-
pation. The memory reference signals (PS, DS, and X/Y) are deasserted (held
high) during periods of no bus activity, and the data signals are three-stated.
For read-modify-write instructions such as BSET, the address and memory
reference signals remain active for the complete composite (i.e., two I
cyc
)
instruction cycle.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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