BUS ARBITRATION AND SHARED MEMORY
MOTOROLA
PORT A
4 - 17
Before BR is asserted, all port A signals are driven. When BR is asserted (see Figure 4-11), the
DSP will assert BG after the current external access cycle completes and will simultaneously
three-state (high-impedance) the port A signals (see the DSP56002 Technical Data Sheet
(DSP56002/D) for exact timing of BR and BG). The bus is then available to whatever external
device has bus mastership. The external device will return bus mastership to the DSP by deas-
serting BR. After the DSP completes the current cycle (an internally executed instruction with or
without wait states), BG will be deasserted. When BG is deasserted, the A0-A15, PS, DS, X/Y,
and RD, WR lines will be driven. However, the data lines will remain in three-state. All signals
are now ready for a normal external access.
During the wait state (see Section 7 in the DSP56000 Family Manual), the BR and BG
circuits remain active. However, the port is inactive - the control signals are deasserted,
the data signals are inputs, and the address signals remain as the last address read or
written. When BR is asserted, all signals are three-stated (high impedance). Table 4-3
shows the status of BR and BG during the wait state.
DSP56002
BUS MASTER
A0 - A15, D0 - D23, PS,
DS, X/Y, RD, WR
BR
BG
A DIFFERENT
BUS MASTER
DSP56002
BUS MASTER
Figure 4-11 Bus Request/Bus Grant Sequence
Signal
Before BR
Asserted
While BG
Asserted
After BR
Deasserted
After Return to
Normal State
(BG Deasserted)
After First
External Access
Table 4-3 BR and BG During WAIT
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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